IJERT-EMS
IJERT-EMS

Analysis of Leakage Power Reduction using Leakage Control Logic with Power Gating


Analysis of Leakage Power Reduction using Leakage Control Logic with Power Gating
Authors : Nikhil Kumar, Rakesh Jain
Publication Date: 02-07-2014

Authors

Author(s):  Nikhil Kumar, Rakesh Jain

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol. 3 - Issue 7 (July - 2014)

e-ISSN:   2278-0181

Abstract

In the world of VLSI Circuits, the semiconductor device length is quickly lowering. Attributable to this the leakage power dissipation has become associate preponderating concern. In this paper power reduction techniques are accustomed scale back power for D-Latch and SR Latch. These techniques involves leakage control Logic, leakage Feedback, sleepy Stacking and Stacking. leakage power is truly consumed once a tool is each static and change, however typically the most concern with leakage power is once the device is in its inactive state , as all the power consumed during this state is taken into account “wasted” power. Power gating which is employed as a basis of this idea is additionally a power reduction technique during which a further “sleep” PMOS transistor is placed between Vdd and also the pull up network of a circuit and a further “sleep” NMOS transistor is placed between the pull down network and GND. These circuits are turned on once the circuit is active and turned off once the circuit is off. Numerous techniques are developed to cut back power leakage. In this paper, the technique which is best in power consumption is obtained which concludes that leakage control logic is able to reduce power more efficiently than other techniques. We have performed the simulation and implementation of all the four above stated techniques on D-Latch and SR-Latch with the help of Tanner Tools.

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