IJERT-EMS
IJERT-EMS

VHDL Implementation of 20-Bit RISC and DSP Operations in FPGA


VHDL Implementation of 20-Bit RISC and DSP Operations in FPGA
Authors : Sethu M
Publication Date: 04-10-2014

Authors

Author(s):  Sethu M

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol. 3 - Issue 10 (October - 2014)

e-ISSN:   2278-0181

Abstract

The Reduced Instruction Set Computer (RISC) is a smaller instruction set used widely in the microprocessors and microcontrollers. By this RISC core is designed to perform some arithmetic operation and perform some DSP operations such as Discrete Cosine Transform (DCT), Inverse Discrete Cosine Tranasform (IDCT) and Fast Fourier Transform (FFT). The design of a Reduced Instruction Set Computer (RISC) and the Digital Signal Processor (DSP) system described using VHDL and is implemented in a Field Programmable Logic Array (FPGA). This 20 bit processor system has high general purpose register (GPR) orthogonality and communicates to peripheral devices via a serial bus.

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