Author(s): Suman Biswas, Dr. J K Das, Rajendra Prasad
Published in: International Journal of Engineering Research & Technology
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Volume/Issue: Vol. 3 - Issue 11 (November - 2014)
Dynamic comparators with high speed , low power and low offset voltage are the main prerequisite features of all ADCs .A low power high speed and low offset dynamic comparator is being introduced in this paper. In all ADC converter architecture the basic building block is a latched comparator. The circuits are simulated in Cadence® Virtuoso Analog Design Environment in GPDK 180nm and 45nm technology. A comparison of the previous architecture and proposed comparator is shown in 180nm. The power consumption of the proposed architecture is 56% lesser than the previous architecture. The Circuit reduces the amount of kickback noise and the offset voltage making it favourable for the pipeline data conversion and flash applications.
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