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Double Gate Tunnel Field Effect Transistor: Review Paper


Double Gate Tunnel Field Effect Transistor: Review Paper
Authors : Mr. Ravish Gupta , Mr. Ravi Mohan, Mr. Divyanshu Rao
Publication Date: 04-09-2015

Authors

Author(s):  Mr. Ravish Gupta , Mr. Ravi Mohan, Mr. Divyanshu Rao

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Volume. 4 - Issue. 09 , September - 2015

e-ISSN:   2278-0181

 DOI:  http://dx.doi.org/10.17577/IJERTV4IS090084

Abstract

Over the last three decades, Complementary metal oxide semiconductor (CMOS) technology developed at unprecedented speed towards a point such that nobody in developed countries can live without that technology. The main building block of CMOS technology is metal oxide semiconductor field effect transistor (MOSFET). To get the low power and high speed technology, device dimension was required to reduce and it was possible. As a result packaging density was increasing and was satisfying the Moore’s statement. But now the trend of decreasing the dimension has reached to its limit. The further reduction of dimension is increasing leakage current. So to combat with these limitations researchers are forced to investigate innovative devices for future technology.

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