A Low-Voltage Low-Power Self Biased Bulk-Driven PMOS Cascode Current Mirror

A Low-Voltage Low-Power Self Biased Bulk-Driven PMOS Cascode Current Mirror
Authors : A. Pramod Kumar, Madhusudan Donga
Publication Date: 05-01-2016


Author(s):  A. Pramod Kumar, Madhusudan Donga

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Volume. 5 - Issue. 01 , January - 2016

e-ISSN:   2278-0181

 DOI:  http://dx.doi.org/10.17577/IJERTV5IS010037


A low-voltage low-power self-biased PMOS cascode current mirror employing bulk driven technique is proposed in this paper. The proposed circuit is analyzed and simulated for various parameters including input/output characteristics, output resistance, current linearity, system dc transmission error, power consumption etc. The circuit is implemented using GPDK 180nm CMOS process and is simulated using Cadence Spectre. The simulation results show that: the proposed bulk driven self-bias cascode current mirror has very high current swing, high output impedance, enhanced current linearity and negligible dc transmission error compared to the high output impedance gate driven current mirrors and bulk-driven current mirrors. Further, with the use of PMOS as the active resistance, the power consumption of the circuit is also reduced drastically. Thus the proposed design finds wide acceptability and usability in low voltage low-power CMOS analog integrated circuits.


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