Author(s): Shaik. Yezazul Nishath, S. Revathi
Published in: International Journal of Engineering Research & Technology
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Volume/Issue: Volume. 5 - Issue. 04 , April - 2016
This paper outlines the design and analysis of the digital phase locked loop (DPLL). It also demonstrates the feasibility of the DPLL in the various applications. The proposed phase frequency detector (PFD) uses 26 transistors analogous to the conventional PFD which uses 54 transistors. It has been observed that the lock in time of the DPLL is very less. In addition to these, an overview on the designing of the charge pump and loop filter is also discussed. Prototype has been designed in Cadence virtuoso environment and implemented using GPDK180 library of 180 nm technology with a supply voltage of 1.8 V.
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