IJERT-EMS
IJERT-EMS

MTCMOS Based 14T SRAM Cell Optimized for High Performance Applications


MTCMOS Based 14T SRAM Cell Optimized for High Performance Applications
Authors : Subham Sriwastava, Kumar Shubham
Publication Date: 31-12-2016

Authors

Author(s):  Subham Sriwastava, Kumar Shubham

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Volume. 6 - Issue. 01 , January - 2017

e-ISSN:   2278-0181

 DOI:  http://dx.doi.org/10.17577/IJERTV6IS010040

Abstract

Static Random Access Memories (SRAM) are designed to provide high speed access and low power consumption to the memory system. Due to aggressive scaling of devices, low power design is extremely important to meet the required constraints. MTCMOS is a technique to achieve low power consumption by employing sleep transistors to reduce the energy requirement of the cell during idle state. The conventional 12T MTCMOS based SRAM cell employs NMOS access transistors. However, this results in a delay and higher power consumption. Hence, a novel MTCMOS based 14T SRAM cell is designed to offer low power consumption with least delay. In the proposed structure, a voltage mode method and TGs are used to reduce the power dissipation. The simulations have been carried out at 45nm CMOS technology, power supply of 1v and a temperature of 𝟐𝟓℃ is taken as a reference. Results show that the power, delay, Power delay product (PDP) and Static Noise Margin (SNM) of the proposed design are improved. Tanner EDA 14.11 is used for the analysis of the circuit and Bsim4v450 model library is used as a tool for simulation.

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