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High Speed DA based Discrete Wavelet Transform Digital Design for Image Processing using Verilog


High Speed DA based Discrete Wavelet Transform Digital Design for Image Processing using Verilog
Authors : Reena S Rajan, Lijesh L
Publication Date: 30-05-2017

Authors

Author(s):  Reena S Rajan, Lijesh L

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Volume. 6 - Issue. 06 , June - 2017

e-ISSN:   2278-0181

 DOI:  http://dx.doi.org/10.17577/IJERTV6IS060016

Abstract

In this paper, the discrete wavelet transform is used and it is the fundamental block in several schemes for image compression. Its implementation relies on filters that usually require multiplications leading to a relevant hardware complexity. Distributed arithmetic is a general and effective technique to implement multiplierless filters and has been exploited in the past to implement the discrete wavelet transform as well. This work proposes a general method to implement a discrete wavelet transform architecture based on distributed arithmetic to produce approximate results. Also here a carry save adder is used in order to reduce the time delay. The novelty of the proposed method relies on the use of result biasing techniques (inspired by the ones used in fixed-width multiplier architectures), which cause a very small loss of quality of the compressed image (average loss of 0.11 dB and 0.20dB in terms of PSNR for the 9/7 and 10/18 wavelet filters, respectively). Compared with previously proposed distributed arithmetic- based architectures for the computation of the discrete wavelet transform, this technique saves from about 20% to 25%of hardware complexity.

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