Author(s): Divya Chandran, Nishi G Nampoothiri
Published in: International Journal of Engineering Research & Technology
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Volume/Issue: Volume. 6 - Issue. 06 , June - 2017
In this project multiple independent FFT computation of two independent data stream is introduced. Multipath delay communicator FFT architecture is the basis of proposed architecture. In time FFT and in frequency FFT it has N/2-point decimation to process the odd and even samples of two data streams separately. The bit reversal operation is performed by the architecture itself is the main feature of the architecture. So without any dedicated bit reversal circuit the outputs are generated in normal order. By interleaving the data the bit reversal operation is performed by the shift registers in the FFT architecture. So high throughput and lower number of register is necessary for the proposed architecture. System throughput is a key factor influencing performance in wireless communication. To increase the transmission rate of the system key research is done.
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