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FPGA Implementation Of Power Efficient Low Latency Viterbi Decoder


FPGA Implementation Of Power Efficient Low Latency Viterbi Decoder
Authors : Nirmal Bhatt, Prof. Milind Shah, Prof. Bhavesh Asodariya
Publication Date: 02-05-2013

Authors

Author(s):  Nirmal Bhatt, Prof. Milind Shah, Prof. Bhavesh Asodariya

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol.2 - Issue 5 (May - 2013)

e-ISSN:   2278-0181

Abstract

Convolution encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolution codes. In this paper, we present a field- programmable gate array implementation of power efficient low latency Viterbi Decoder with a constraint length of 7 and a code rate of 1/2.We also proposed One Pointer algorithm for Trace back Implementation of survivor sequence memory management for low power decoder design.

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