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Design of 6 Bit Vedik Multiplier using Vedik Sutra


Design of 6 Bit Vedik Multiplier using Vedik Sutra
Authors : Yashkumar . M . Warkari, Prof L. P. Thakre, Dr. A. Y. Deshmukh
Publication Date: 10-04-2014

Authors

Author(s):  Yashkumar . M . Warkari, Prof L. P. Thakre, Dr. A. Y. Deshmukh

Published in:   International Journal of Engineering Research & Technology

License:  This work is licensed under a Creative Commons Attribution 4.0 International License.

Website: www.ijert.org

Volume/Issue:   Vol. 3 - Issue 4 (April- 2014)

e-ISSN:   2278-0181

Abstract

The tenets of mathematics is existing since from long time which is in time span of years together. Related to the several kinds of fundamental mathematical necessities during technical sorting &processing with various categories of data for processing . In order to heed & step out from such facing difficult situations, some expertise had explained the mathematical tenets during ancient times. Later on the absolutely important things drawn out by expertise arduously which collectively produce the helpful tool named as vedic mathematics. The main aim of the project is to improve the speed of the multiplier by using vedic mathematics . The 6*6 bit vedic multiplier is the proposed design of this paper.

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