Author(s): Uday Arun, A. K. Sinha, K.S. Yadav
Published in: International Journal of Engineering Research & Technology
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Volume/Issue: Vol.1 - Issue 7 (September - 2012)
Power-awareness indicates the scalability of the system energy with changing conditions and quality requirements. Multipliers are essential elements used in DSP applications and computer architectures. Although Boolean multipliers have natural power awareness to the changing of input precision, deeply pipelined designs do not have this benefit. A Single-Edge-Triggering (SET) & Double- Edge-Triggering (DET) one-dimensional pipeline gating scheme is proposed to improve the speed, the power awareness and area in designs. In one- dimensional pipeline, clock the registers (D-FF) at both edges i.e. positive as well negative (data flow in pipeline) and horizontal direction (within each pipeline stage). This technique only needs very little additional area and the overhead is hardly noticeable. A set of Hybrid Multiplier were designed and tested. Results show that the new 32- bit Hybrid Multiplier using this technique has low power and high speed at lower clock frequency as compare to other designs.With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on- chip. One of the more effective and widely used methods for power aware computing is Dynamic Voltage Scaling (DVS). In order to obtain the maximum power savings from DVS, it is essential to scale the supply voltage as low as possible while ensuring correct operation of the processor. The critical voltage is chosen such that under a worst case scenario of process and environmental variations, the processor always operates correctly. However, this approach leads to a very conservative supply voltage since such a worst case combination of different variability will be very rare. A SET & DET D-flip-flop pipeline multiplier pipeline Hybrid Multiplier design will work at the clock frequency in the range of 50MHz to 250MHz and SET based pipeline Hybrid Multiplier design will work at the clock frequency in the range of 50MHz to 500MHz. We have used hyper-pipelining approach in pipeline design by changing register- retiming approach i.e. combined memory at DET to further improve the speed as well as area & power consumption. The various design & analysis presented in result section.
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