Design and Implementation of Urdhva-Tiryakbhyam Based Fast 8×8 Vedic Binary Multiplier

Design and Implementation of Urdhva-Tiryakbhyam Based Fast 8×8 Vedic Binary Multiplier

Amrita Nanda

Final Year Student, M.Tech (VLSI), ECE Department.

CIT, Centurion University of Technology & Management

Jatni (Odisha), India

Shreetam Behera

Asst.Professor, ECE Department.

CIT, Centurion University of Technology & Management

Jatni (Odisha), India

Abstract This paper depict the design of an efficient 8×8 binary arithmetic multiplier by using Vedic Mathematics. From various multiplication techniques, Urdhva-Tiryakbhyam sutra is being implemented because this sutra is applicable to all cases of algorithm for N×N bit numbers and the minimum delay is obtained. A 4×4 Vedic Multiplier is designed using a special 4- bit adder which is having reduced delay. The 8-bit multiplier is designed using four 4-bit multiplier and special designed adders. The computational path delay obtained is less in comparison to Array multiplier and Booth multiplier. The 8×8 Vedic Multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE14.4 Software.

Keywords: Vedic Mathematics, Urdhva-Tiryakbhyam, Vedic Multiplier , VHDL.

I .INTRODUCTION

Vedic mathematics is the name given to the ancient system of mathematics which was rediscovered from the Vedas. In compare to conventional mathematics Vedic mathematics is simpler and easy to understand. Swami Bharati Krishna Tirthaji Maharaj (1884-1960), re-introduced the concept of ancient system of Vedic mathematics [5].

The word 'Vedic' is resultant from the word 'Veda' which means the store-house of all knowledge. Vedic mathematics includes sixteen-sutras or formulae and thirteen sub-sutras. Various applications of Vedic mathematics includes theory of numbers, compound multiplication, algebraic operation, calculus, squaring, cubing, cube root, simple quadratic, coordinate geometry and wonderful Vedic Numeric Code .

Vedic mathematics is a domain which presents various effective algorithms that can be applied in different branches of engineering such as digital signal processing and computing. Most common multiplication algorithms in math coprocessor are array and booth multiplication algorithm. Due to the parallel calculation of the partial products the array

multiplier takes less computation time. For high speed multiplication large booth arrays having partial sum and carry register is required [4].

An 8-bit multiplier is designed using a 4-bit multiplier and ripple carry adders is discussed in [1]. The number of logic levels and logic delay is being reduced using the Urdhva- Tiryakbhyam sutra. Total delay obtained is less in comparison to other Vedic multiplier designs.

In [2], authors provide a study on high speed 8×8 bit Vedic multiplication architecture which is different from the conventional mathematics of multiplication like add and shift as in [13,14]. A 4×4 multiplier has been designed and implemented in [8] by the help of 6-bit special adder has been proposed for binary multiplication. Similarly in [4], a 32×32 multiplier is proposed for binary multiplication.

Authors have compared implementation of normal multiplication and Vedic multiplication. They claim that same number of multiplication and addition operations is required in both normal multiplier and Vedic multiplier. They have tested and compared various multiplier implementations such as Array multiplier, Multiplier macro, Vedic multiplier with full partitioning, Vedic multiplier using 4 bit macro, fully recursive Vedic multiplier, and Vedic multiplier using 8 bit macro for optimum speed [6]. In [7, 9, 10] implementation of binary multiplication in different applications has been discussed.

In this paper, the multiplication operation is being carried out using Urdhva-Tiryakbhyam sutra in binary, and the design is implemented using VHDL language. The following paper is structured as follows: Section II describes the Urdhva-Tiryakbhyam method. Section III explains the proposed 8×8 Vedic multiplier where as the result is discussed in Section IV followed by conclusion and references in Section V and VI.

II .URDHVA-TIRYAKBHYAM METHOD

The word Urdhva-Tiryakbhyam means vertical and crosswise multiplication. This multiplication formula is applicable to all cases of algorithm for N bit numbers [6]. Traditionally the sutra is used for the multiplication of two numbers in decimal number system. The same concept can be applicable to binary number system which is being discussed in this paper. Advantage of using this type of multiplier is that as the number of bits increases, delay and area increases very slowly as compared to other multipliers.

Fig.1 Multiplication method of Urdhva-Tiryakbhyam

In the above figure, 4-bit binary numbers A0A1A2A3 and B0B1B2B3 are considered. The result obtained is stored in R0R1R2R3R4R5R6R7.In the first step [A0, B0] is multiplied and the result obtained is stored in R0. Similarly in second step [A0, B1] and [A1, B0] are multiplied using a full adder and the sum is stored in R1 and carry is transferred to next step. Likewise the process continues till we get the result.

1. .PROPOSED TECHNIQUE

   The 4×4 multiplier in binary is implemented using VHDL. For reducing the delay of 4×4 multiplier, it is implemented using two half adders, seven full adders and a 4-bit adder.

   Fig 2 Architecture of Urdhva-Tiryakbhyam 4×4 multiplier

   The 4-bit adder is designed for 4×4 Vedic Multiplier in which four input can be given and three output is generated, out of which one is sum and rest two are carry. The 8×8 Vedic multiplier is designed using four 4×4 Vedic multipliers which employs Urdhva-Tiryakbhyam method. The output of these Vedic multipliers is added by modifying the logic levels of ripple carry adder [5]. The 8-bit input sequence is divided into two 4-bit numbers and given as inputs to the 4-bit multiplier blocks A [7-4] & B [7-4], A [3-0] & B [7-4], A [7-

   4] & B [3-0], A [3-0] & B [3-0]. The LSB product bits R [3- 0] is directly obtained from one of the multipliers. The second and third multiplier block output is added directly using ADDER-1 as the second and third region is overlapping. The higher order bit of first multiplier block is added to the overlapping sum using ADDER-2 which gives the product R [7-4]. Lastly, MSB bits R [15-8] is obtained by adding the fourth multiplier output to the carry from ADDER-1 (added at the fifth bit position) and higher order bits of ADDER-3 [3]. Block diagram of the proposed 8×8 multiplier is illustrated in figure.

   Fig 3 Architecture of 8×8 Vedic Multiplier

2. .RESULT & SIMULATION

   Here the RTL-Schematic, test bench waveform, device utilization summary are shown, which are generated using Xilinx ISE14.4 version.

   Fig 4 RTL Schematic of 4×4 Vedic Multiplier

   Fig 5 RTL Schematic of 8×8 Vedic Multiplier

   Fig 6 Technology Schematic of 4×4 Vedic Multiplier

   Fig 7 RTL Schematic of 8×8 Vedic Multiplier

   Fig 8 Test bench Waveform of 8×8 Vedic Multiplier (Input)

   Fig 9 Test bench Waveform of 8×8 Vedic Multiplier (Output)

   TABLE-I Device Utilization Summary

   Number of Slices:	91 out of 960 9%
   Number of 4 input LUTs:	161 out of 1920 8%
   Number of IOs:	32
   Number of bonded IOBs:	32 out of 66 48%

3. .CONCLUSION

A highly efficient method of multiplication, Urdhva- Tiryakbhyam Sutra bsed on Vedic mathematics is presented in this paper. The code has been simulated on Xilinx ISE 14.4 version, and implemented on Spartan 3e FPGA board. Tough Vedic Mathematics provides various Sutras, but their application to the field is not completely studied. The proposed Vedic multiplier is faster than Array and Booth multiplier in terms of execution time.

VI. REFERENCES

1. Krishnaveni D, Umarani T.G, VLSI Implementation of Vedic Multiplier With Reduced Delay, IJATER, NCET-Tech, ISSN No:- 2250-3536, Volume 2, Issue 4, July 2012.

2. Poornima M, Shivaraj Kumar Patil, Shivu kumar, Shridhar KP, Sanjay H, Implementation of Multiplier Using Vedic Algorithm, IJITEE,ISSN:-2278-3075,Volume-2,Issue-6,May-2013.

3. Premananda B.S, Samarth S. Pai, Shashank B, Shashank S.Bhat, Design And Implementation of 8-bit Vedic Multiplier, IJAREEIE,Vol.2,Issue 12,ISSN:2320-3765,Dec-2013.

4. S.Kokila, Ramadhurai.R,L.Sarah, VHDL Implementation of Fast 32 X 32 Multiplier based on Vedic Mathematics, International Journal of Engineering Technology and Computer Applications, Vol.2,No.1,April 2012.

5. Swami Bharati Tirtha, Vedic Mathematics. Delhi: Motial Banarsidass Publishers, 1965.

6. P. Mehta, D. Gawali, Conventional versus Vedic Mathematical Method for Hardware Implementation of a

   Multiplier, International Conf. on Advances in Computing, Control, and Telecommunication Technologies, Trivandrum, Kerala, India, pp. 640-642, 2009.

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8. A Nanda, S R Panigrahi, S Behera, Design and Validation of a 4×4 Vedic Multiplier on Xilinx Spartan 3E FPGA,

   VLSI Signal Processing and Trends in Telecommunication (VS@TT13) 19th -20th April 2013.

9. S. Shanthala, C.P. Raj, Design and VLSI Implementation of Pipelined Multiply Accumulate Unit, International Conference on ETET-09, pp 381-386, 2009.

10. K Shin, I K Oh, S Min, B S Ryu, K Y Lee and T W Cho A Multi- Level Approach to Low Power Mac Design IEEE Trans.VLSI systems, vol-48 , pp 361- 763, 1999.

11. V. A. Pedroni,Circuit Design with VHDL, MIT Press, Cambridge, 2008.

12. D L Perry, VHDL: Programming by Example, McGraw-Hill Publications, New Delhi, 2002.

13. M.Morris Mano, Michael D.Ciletti, Digital Design with an Introduction to the Verilog HDL, Pearson, 5th edition, 2013.

14. Floyd & Jain, Digital Fundamentals, Pearson Education, 8th edition, 2009.

AUTHORS PROFILE

Shreetam Behera is presently working as Assistant Professor in the Department of ECE at Centurion University of Technology and Management, Jatni,Odisha. He passed his Masters in Technology in Electronics and Instrumentation Engineering from the Siksha O Anusandhan University, Bhubaneswar, Odisha in the year 2012 .He did his Bachelor Of Technology in Electronics and Communication engineering in the year 2010 from Gandhi Institute of Engineering and Technology, Gunupur, Rayagada, Odisha, India. His research areas include Image Processing, Signal Processing and Embedded Systems.

Amrita Nanda obtained her B.Tech degree in Electronics and Communication Engineering branch from NMIET in the year 2010. Currently she is a final year M.Tech student in VLSI specialization at Centurion University. She published a conference paper named Design and Validation of a 4×4 Vedic Multiplier on Xilinx Spartan 3E FPGA.