Architectural Low Power Implementation of UART using Verilog

Architectural Low Power Implementation of UART using Verilog

Mohammed Azeemuddin, Prof. S.K Ahmeduddin Zakir

Shadan College of Engineering and Technology Hyderabad, India

Abstract – UART is Universal Asynchronous Receiver Transmitter. It is mostly used for short-distance, low speed, low-cost data exchange between peripherals. The UART allows the devices to communicate without need to be synchronized. In this project we try to minimize the power consumption by using low power techniques. With the proliferation of portable electronic devices, power efficient data transmission has become increasingly important. Components such as laptop, keyboards, palmtops and modems are few examples of devices that employ UART circuits. In this project we are enhancing IEEE paper in which a normal UART is synthesized and results are simulated using Xilinx then these files are run under Power compiler tool to find power consumption by normal UART and then by using two techniques of low power we reduce power consumption which is shown in the power reports. The UART is implemented using Verilog which is having more advantages as compared to VHDL.

1. INTRODUCTION

   An UART (universal asynchronous receiver / transmitter) is responsible for performing the main task in serial communications with computers. The device changes incoming parallel information to serial data which can be sent on a communication line. A second UART can be used to receive the information. The UART performs all the tasks, timing, parity checking, etc. needed for the communication. The only extra devices attached are line driver chips capable of transforming the TTL level signals to line voltages and vice versa.

   To use the device in different environments, registers are accessible to set or review the communication parameters. Setable parameters are for example the communication speed, the type of parity check, and the way incoming information is signaled to the running software.

   The serial port on your PC is a full-duplex device meaning that it can send and receive data at the same time. In order to be able to do this, it uses separate lines for transmitting and receiving data. Some types of serial devices support only one-way communications and therefore use only two wires in the cable – the transmit line and the signal ground.

   Figure 1 Format of data transfer in UART

   Once the start bit has been sent, the transmitter sends the actual data bits. There may either be 5, 6, 7, or 8 data bits, depending on the number you have selected. Both receiver and the transmitter must agree on the number of data bits, as well as the baud rate. Almost all devices transmit data using either 7 or 8 databits. As shown in figure start bit is low and stop bit is high, when data bits plus start bit is transferred counter identifies number of data bits then checks for stop bit and when encountered it will stop transmission.

   Notice that when only 7 data bits are employed, you cannot send ASCII values greater than 127. Likewise, using 5 bits limits the highest possible value to 31. After the data has been transmitted, a stop bit is sent. A stop bit has a value of 1 – or a mark state – and it can be detected correctly even if the previous data bit also had a value of 1. This is accomplished by the stop bit's duration. Stop bits can be 1, 1.5, or 2 bit periods in length.

2. IMPLEMENTATION

   In this paper, the top to bottom design is used. The UART serial communication is divided into three sub- modules: the baud generator, receiver module and transmitter module. Therefore, the implementation of the UART communication module is actually the realization of the three sub-modules. The baud generator is used to produce a local clock signal which is much higher than the baud rate to control the UART receive and transmit module. The receiver module is used to receive the serial signals and convert them into parallel data. The UART transmit module converts the bytes into serial bits according to the basic frame format and transmit those bits.

   Baud Generator

   Here we want to use the serial link at maximum speed, i.e. 115200 bauds. Other slower speeds would also be easy to generate. It is responsible to generate bauds for the transmitter and receiver modules one is 16 times other is 8 times.

   FPGAs usually run at speed well above 115200Hz (RS-232 is pretty slow by today's standards). That means we use a high-speed clock and divide it down to generate a "tick" as close as possible to 115200 times a second.

   Transmitter Module

   Once the "start" bit is detected, we sample the line at the known baud rate to acquire the data bits.

3. LOW POWER TECHNIQUES USED

   In this paper we have used two techniques that is voltage scaling and Module Powerdown, apart from these two we have many techniques like Clock gating, MT-CMOS, LT-ASCII and Data stream dependent shutdown.

   Voltage Scaling

   In this technique we are going to reduce the supply voltage itself which will reduces the power consumption as power is related to supply voltage as shown in below equation.

   P fclk CL Vdd2

   Where is the activity factor, fclk is the operating frequency, CL is the load capacitance and Vdd is the supply voltage.

   that

   Figure 2 Transmitter module

   We are building an "async transmitter" and it works like

   • The transmitter takes 8-bits data, and serializes it (starting when the "TxD_start" signal is asserted).

   • The "busy" signal is asserted while a transmission occurs. The "TxD_start" signal is ignored during that time.

     Module Powerdown

     In this technique we use to turn off the module like receiver when baud generator and transmitter are working and viceversa. As shown in above equation again power is directly proportional to square of voltage and this voltage is equal to sum of the all three module voltages.

4. RESULTS AND DISCUSSIONS

   After synthesizing the top module of UART in Xilinx software we get the schematic of the RTL as shown

   in below diagram.

   The RS-232 parameters used are fixed: 8-bits data, 2 stop bits, no-parity.

   Receiver Module

   Figure 3 Receiver Module

   We are building an "async receiver" and our implementation works like that:

   • The module assembles data from the RxD line as it comes.

   • As a byte is being received, it appears on the "data" bus. Once a complete byte has been received, "data_ready" is asserted for one clock.

     An asynchronous receiver has to somehow get in-sync with the incoming signal (it doesn't have access to the clock used during transmission).

   • To determine when a new data is coming ("start" bit), we oversample the signal at a multiple of the baud rate frequency.

   Figure 4 Schematic of Top level UART after synthesis

5. SIMULATION

After synthesizing the code let us now simulate the baud generator in a Xilinx Simulator, the waveform is as shown below which produces two bauds one for transmitter module and another for receiver module which is oversampled.

Figure 5 waveform of Baud Generator

Next is transmitter module to which parallel input is applies and it produces serial output which can be seen in

the below simulation result.

Figure 6 waveform of Transmitter Module

At the Receiver side the serial data is acting as an input and the output of this will be parallel data as shown in below simulation aveform.

Figure 7 Waveform of Receiver Module

Table 1 Comparison of normal UART with Low power UART

Power Report of Top UART (low)

We run the top module Verilog files in the power compiler tool by reducing power supply voltage and it generates power reports.

Figure 8 Power report of Top UART (low)

1. CONCLUSION

   • Several low power configurations were examined to minimize the UART power consumption. But for our project we used only two techniques that is voltage scaling and module powerdown because power analyzation is quite easy in this case.

   • No doubt other techniques are also very useful but we are restricted to academically possible techniques.

   • With voltage scaling practically we saved approximately 84% of power and in case of module power down it is approximately 89% of power consumption is reduced.

   • Future of this UART also depends on the advancement in low power design which may reduce much more power consumption.

2. REFERENCES

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