Design of Higher Level Back-to-Back Stacked Multicell Converter with DMPG Control Technique to Improve the Power Quality

DOI : 10.17577/IJERTV3IS061421

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Design of Higher Level Back-to-Back Stacked Multicell Converter with DMPG Control Technique to Improve the Power Quality

Vijaya raju Vasipalli, PG scholar

Dept. of Electrical Engineering SATI, Vidisha, Madhya Pradesh, India

Ashok Kumar Patel,

PG scholar

Dept. of Electrical Engineering SATI, Vidisha, Madhya Pradesh, India

Praveen Pateriya,

PG scholar

Dept. of Electrical Engineering SATI, Vidisha, Madhya Pradesh, India

Abstract – This paper proposes the new Back-to-Back Stacked Multicell Converter with DMPG control technique. In this paper we designed 4-cell 17-Level BTB-SMC and 8-cell 49-Level BTB-SMC. Both converters are control by DMPG control technique only. Both converters are compared in their design and power quality. Whenever the number of output voltage levels are increase then the harmonics will decrease so that power quality is good. This paper also explains DMPG technique, which is very suitable technique to generate control pulses for any circuit. Circuits are designed in MATLAB/SIMULINK software.

KeywordsBack-to-Back Stacked Multicell Converter (BTB- SMC), Degree Modulated Pulse Generation (DMPG).

  1. INTRODUCTION

    In recent years the multilevel concept is widely using in high power high/medium voltage applications because when the levels of output waveform is increase then the harmonic content in the output waveform will decrease so the power quality will increase.

    There are so many concepts on multilevel but flying capacitor Multicell (FCM) converter and stacked Multicell (SM) converters are advanced technologies for multilevel generation [1]. FCM converter can convert DC/AC or DC/DC [2].SM converter is more efficient than Hybrid FCM converter [3]. The word Back-to-Back is defined that two semiconductor switches are connected in back to back position.

  2. MULTICELL CONCEPT

    One DC source and two semiconductor switches formed as one cell. Two semiconductor switches connected back to back with DC source.

    First I would like to Thank my guide Prof. S.P Phulambrikar (HOD) for his great guidance and motivation.

    I would like to thank my friends Vikalp Kulshrestha & Ankur Chourasiya for their heartful help.

    I thank to all Faculty members who helped me. Especially to Mr. Rakesh Sagar sir who did software installation for me.

    Finally I thank to my loving family members who always supported me, encouraged me, and motivated me.

    Fig.1. Block Diagram of SMC

    As we seen in the Fig.1 the circuit which is connected with Number of Cells is called as Multicell converter.

    There are two types of cells in the SMC circuit one is P-cell another one is N-cell. The combinations of these cells are called as Multicell. Derivative of FCM converter is SM converter. To increase the output voltage levels we uses m× n cells array [1].

  3. THE PROPOSED CONVERTER

    As shown in the bellow Fig. two SM converters are connected back to back each other in proposed BTB-SM converter. Both converters are separated with two switches T1 & T2 [1]

    With the help of T1 & T2 we can produce positive and negative half cycles respectively.

    Number of cells and output voltage levels are calculated by: N cell =2(n + m) (1)

    N Level =2[(2n+1) (2m+1)]-1.. (2)

    The voltage values for proposed converter are calculated by: Ea = [2n (2m+1)/((2n+1)(2m+1)-1)]×E . (3)

    Eb = E – Ea.. (4)

    Where E is maximum output voltage.

    Fig.2. 2(n + m) cell proposed converter block diagram

    Fig.3. SIMULINK diagram of 4-cell, 17-Level converter

    Fig.4. SIMULINK diagram of 8-cell, 49-Level converter

    1. Proposed 4-cell, 17-Level Converter

      As shown in the Fig. BTB-SMC consists of two converters connected back to back with the help of two switches T1 & T2. The SMC, which is right side to the T1 & T2, consists of n cells and The SMC, which is left side to the T1 & T2, consists of m cells. Each cell in the both SMCs has two sub-cells one is P-cell and another one is N-cell. In each converter Number of P-cells is equal to number of N-cells.so right side converter has 2n-cells and left side converter has 2m-cells.

      In 4-cell converter n=1 and m=1 so the number of cells and levels are calculated by:

      N Cell =2(n + m) =4-cell. (5)

      N Level =2[(2n+1)(2m+1)]-1 =17-Level. (6)

    2. Proposed 8-cell, 49-Level Converter

    As explained in the above portion 49-Level converter has 8- cells this is calculated from equations 1 & 2. In this converter n=2 and m=2. When the number of cells are increasing then the number of output voltage levels are increase. The converter which is for any Level has four voltage sources. When number of output voltage levels are increasing then the flying capacitors and switches will increase.

  4. CONTROL TOPOLOGIES

    1. DMPG Technique for 17-Level Converter

      Fig.5. DMPG Circuit

      Output Voltage Levels

      Switching States

      T1

      T2

      (S11 S21 S12 S22)

      +E

      1

      0

      (1 1 1 1)

      +7E/8

      1

      0

      (1 1 1 0)

      +6E/8

      1

      0

      (1 1 0 0)

      +5E/8

      1

      0

      (0 1 1 1)

      +4E/8

      1

      0

      (0 1 0 1)

      +3E/8

      1

      0

      (0 1 0 0)

      +2E/8

      1

      0

      (0 0 1 1)

      +1E/8

      1

      0

      (0 0 0 1)

      TABLE I. SWITCHING STATES FOR 17-LEVEL SMC

      0

      1

      0

      (0 0 0 0)

      0

      1

      (1 1 1 1)

      -1E/8

      0

      1

      (1 1 1 0)

      -2E/8

      0

      1

      (1 1 0 0)

      -3E/8

      0

      1

      (1 0 1 1)

      -4E/8

      0

      1

      (0 1 0 1)

      -5E/8

      0

      1

      (0 1 0 0)

      -6E/8

      0

      1

      (0 0 1 1)

      -7E/8

      0

      1

      (0 0 0 1)

      -E

      0

      1

      (0 0 0 0)

      Degree modulation or sector selection:

      N Sectors = (2×N Levels) + 2 (7) Each sector = (360÷ N Sectors) °. (8)

      After generation of Degree modulated control signal we give it to multi port switch to select the suitable switching state.

      Fig.6. Control signal for the multiport switch

      Fig.7. Switching pulses for 17-Level Converter

    2. DMPG Technique for 49-Level Converter

    Output Voltage Levels

    Switching States

    T1

    T2

    (S11 S21 S1II S2II S12 S22 SI2 SII2)

    +E

    1

    0

    (1 1 1 1 1 1 1 1 )

    +23E/24

    1

    0

    (1 1 1 10 1 1 1 )

    +22E/24

    1

    0

    (1 1 1 1 0 0 1 1 )

    +21E/24

    1

    0

    (1 1 1 1 0 0 0 1 )

    +20E/24

    1

    0

    (1 1 1 1 0 0 0 0 )

    +19E/24

    1

    0

    (0 1 1 1 1 1 1 1 )

    +18E/24

    1

    0

    (0 1 1 1 0 1 1 1 )

    +17E/24

    1

    0

    (0 1 1 1 0 0 1 1 )

    +16E/24

    1

    0

    (0 1 1 1 0 0 0 1 )

    +15E/24

    1

    0

    (0 1 1 1 0 0 0 0 )

    +14E/24

    1

    0

    (0 1 0 1 1 1 1 1 )

    +13E/24

    1

    0

    (0 1 0 1 0 1 1 1 )

    +12E/24

    1

    0

    (0 1 0 1 0 0 1 1 )

    +11E/24

    1

    0

    (0 1 0 1 0 0 0 1 )

    +10E/24

    1

    0

    (0 1 0 1 0 0 0 0 )

    +9E/24

    1

    0

    (0 0 0 1 1 1 1 1 )

    +8E/24

    1

    0

    (0 0 0 1 0 1 1 1 )

    +7E/24

    1

    0

    (0 0 0 1 0 0 1 1 )

    +6E/24

    1

    0

    (0 0 0 1 0 0 0 1 )

    +5E/24

    1

    0

    (0 0 0 1 0 0 0 0 )

    +4E/24

    1

    0

    (0 0 0 0 1 1 1 1 )

    +3E/24

    1

    0

    (0 0 0 0 0 1 1 1 )

    +2E/24

    1

    0

    (0 0 0 0 0 0 1 1 )

    +1E/24

    1

    0

    (0 0 0 0 0 0 0 1 )

    0

    1

    0

    (0 0 0 0 0 0 0 0 )

    0

    0

    1

    (1 1 1 1 1 1 1 1 )

    -1E/24

    0

    1

    (1 1 1 1 1 1 1 0 )

    -2E/24

    0

    1

    (1 1 1 1 1 1 0 0 )

    -3E/24

    0

    1

    (1 1 1 1 1 0 0 0 )

    -4E/24

    0

    1

    (1 1 1 1 0 0 0 0 )

    -5E/24

    0

    1

    (1 1 1 0 1 1 1 1 )

    -6E/24

    0

    1

    (1 1 1 0 1 1 1 0 )

    -7E/24

    0

    1

    (1 1 1 0 1 1 0 0 )

    -8E/24

    0

    1

    (1 1 1 0 1 0 0 0 )

    -9E/24

    0

    1

    (1 1 1 0 0 0 0 0 )

    -10E/24

    0

    1

    (1 0 1 0 1 1 1 1 )

    -11E/24

    0

    1

    (1 0 1 0 1 1 1 0 )

    -12E/24

    0

    1

    (1 0 1 0 1 1 0 0 )

    -13E/24

    0

    1

    (1 0 1 0 1 0 0 0 )

    -14E/24

    0

    1

    (1 0 1 0 0 0 0 0 )

    -15E/24

    0

    1

    (1 0 0 0 1 1 1 1 )

    -16E/24

    0

    1

    (1 0 0 0 1 1 1 0 )

    -17E/24

    0

    1

    (1 0 0 0 1 1 0 0 )

    -18E/24

    0

    1

    (1 0 0 0 1 0 0 0 )

    -19E/24

    0

    1

    (1 0 0 0 0 0 0 0 )

    -20E/24

    0

    1

    (0 0 0 0 1 1 1 1 )

    -21E/24

    0

    1

    (0 0 0 0 1 1 1 0 )

    -22E/24

    0

    1

    (0 0 0 0 1 1 0 0 )

    -23E/24

    0

    1

    (0 0 0 0 1 0 0 0 )

    -E

    0

    1

    (0 0 0 0 0 0 0 0 )

    TABLE II. SWITCHING STATES FOR 49-LEVEL SMC

    Calculate degree modulation or sector selection by using Equations 7 & 8. With the comparison of ramp signal and degree modulated generated signal the control signal will generate. We will give this control signal to the multiport switch to select the suitable sector.

    Fig.8. Control signal for the multiport switch

    Fig.9a. Switching pulses for 17-Level Converter

    Fig.12. Output Voltage and Current of 17-Level Converter with Filter

    Fundamental (50Hz) = 215.3 , THD= 6.12%

    6

    Mag (% of Fundamental)

    5

    4

    3

    2

    1

    0

    0 2 4 6 8 10 12 14 16 18

    Harmonic order

    Fig.9b. Switching pulses for 49-Level Converter

    6

    Mag (% of Fundamental)

    5

    4

  5. SIMULATION RESULTS

3

  1. Proposed 4-cell, 17-Level Converter 2

    Fundamental (50Hz) = 21.53 , THD= 6.12%

    1

    0

    0 2 4 6 8 10 12 14 16 18 2

    Harmonic order

    Fig.13. FFT window of Output Voltage and Current

    Fig.10. Output Voltage and Current of 17-Level Converter without Filter

  2. Proposed 8-cell, 49-Level Converter

    Fundamental (50Hz) = 166 , THD= 15.79%

    16

    14

    Mag (% of Fundamental)

    12

    10

    8

    6

    4

    2

    0

    0 2 4 6 8 10 12 14 16 18 2

    Harmonic order

    Fig.11a. FFT window of Output Voltage

    Fundamental (50Hz) = 16.6 , THD= 15.79%

    16

    14

    Mag (% of Fundamental)

    12 Fig.14. Output Voltage and Current of 49-Level Converter without Filter

    10

    8

    6

    4

    2

    0

    Fig.11b. FFT window of Output Current

    Fig.15. FFT window of Output Voltage and Current without Filter

    Fig.16. Output Voltage and Current of 49-Level Converter with Filter

    Fig.17. FFT window of Output Voltage and Current with Filter

    1. COMPARISION OF 17 AND 49- LEVEL CONVERTERS

      TABLE III. 17 Vs 49- LEVEL COMPARISION

      System Parameters

      17-Level

      49-Level

      No. of switches

      4(back to back)

      8(back to back)

      E, Ea& Eb

      200, 150& 50V

      600, 500& 100V

      DC Voltage sources

      4

      4

      Flying Capacitors

      0

      4

      Load Resistance

      10

      10

      THD (%) without Filter

      15.79%

      13.37%

      Voltage Mag. at fundamental freq.

      166V

      490.7V

      Current Mag. at fundamental freq.

      16.6A

      49.07A

      THD (%) with Filter

      6.12%

      5.15%

      Voltage Mag. at fundamental freq.

      215.3V

      635.4V

      21.53A

      63.54A

    2. CONCLUSSIONS

    Multi level concept is very popular in recent years because if the number of output voltage levels are increase then the harmonics of the converer will decrease [5]. So that there are so many multi level concepts are there but the back to back stacked Multicell converter is very new proposed topic to improve the power quality. As we seen in the comparison of both 17 and 49- level converters we can say that 49-Level BTB-SMC is more better than 17-Level BTB-SMC. Results are analyzed in FFT Window.

    REFERENCES

    1. Mohammad Ali Hosseinzadeh, Ebrahim Babaei, Member, IEEE, Mehran Sabahi Back-to-Back Stacked Multicell Converter IEEE Catalog Number: CFP121IJ-ART, ISBN: 978-1-4673-0113- 8/12/$31.00 ©2012 IEEE

    2. Alex Ruderman, Boris Reznikov , and Michael Margaliot Analysis of a Flying Capacitor Converter: A Switched Systems Approach 13th International Power Electronics and Motion Control Conference (EPE PEMC'08), Poland, 2008.

    3. M. R. Banaei, F. Mohajel kazemi A Modified Selective Harmonic Elimination switching strategy for Hybrid Flying Capacitor Multicell Converter ELECO 2011 7th International Conference on Electrical and Electronics Engineering, 1-4 December, Bursa, TURKEY

    4. Ruzlaini Ghoni,Ahmed N. Abdalla "Analysis And Mathematical Modelling Of Space Vector Modulated Direct Controlled Matrix Converter" Journal of Theoretical and Applied Information Technology

      © 2005 – 2010 JATIT. All rights reserved.

    5. l Rodriguez, lS. Lai, and F.Z. Peng, "Multilevel inverters: A survey of topologies, controls, and applications," IEEE Trans. Ind Electron., voL 49, no. 49, pp. 724-738, August 2002.

    6. 1. A Meynard, H. Foch, P. Thomas, l Courault, R. Jakob, andM Nahrstaedt, "Multicell converters: Basics concepts and industry applications," IEEE Trans. Ind. Electron., voL 49, no. 5, pp. 955- 964, Oct 2002.

    7. Vahid Dargahi and Abbas Shoulaie " Capacitors Natural Voltage Balancing Mechanism Investigation in Flying Capacitor Multicell Converters" International Electrical Engineering Journal (IEEJ) Vol. 3 (2012) No. 2, pp. 738-744 ISSN 2078-2365.

    8. Amal Philomiya L, Saravanan.C, Narasimman.P " Performance Analysis of Improved Double Flying Capacitor Multicell Converter" International Journal of Emerging Technology and Advanced Engineering Website: www.ijetae.com (ISSN 2250-2459, ISO 9001:2008 Certified Journal, Volume 3, Issue 7, July 2013).

    9. Meisam Sadeghi, Mojtaba Khederzadeh " Half-cell Flying Capacitor Multicell converter: a Reduced Number of Switches Topology" 28 th Power System Conference – 2013 Tehran, Iran No. E-13-AAA-0000.

    10. A.M. Lienhardt, G. Gateau, T.A. Meynard "Stacked Multicell Converter (SMC): Reconstruction of flying capacitor voltages" Laboratoire dElectrotechnique et dElectronique Industrielle – UMR INPT-ENSEEIHT / CNRS BP 7122 2, rue Camichel 31071 TOULOUSE Cedex 7 – FRANCE.

    11. Samir Kouro, Mariusz Malinowski, K. Gopakumar, Josep Pou, Leopoldo G. Franquelo, BinWu, Jose Rodriguez, Marcelo A. Pérez, Jose I. Leon " Recent Advances and Industrial Applications of Multilevel Converters" IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 8, AUGUST 2010

    12. T.Govindaraj and A.Nandhini " An Improved Double Flying Capacitor Multicell Converter Controlled By a Phase-Shifted Carrier PWM" International Journal of Advanced and Innovative Research (2278- 7844) / # 233 / Volume 3 Issue 2

    13. O. Benzineb, F. Taibi, M.E.H. Benbouzid, M.S. Boucherit and M. Tadjine " Multicell Converters Hybrid Sliding Mode Control Author manuscript, published in "International Review on Modelling and Simulations 4, 4 (2011) 1396-1403"

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