Design and Optimization of Asynchronous counter using Reversible Logic

Design and Optimization of Asynchronous counter using Reversible Logic

Mr Harish k

PG scholar Department of ECE, RVCE

RVCE , Bengaluru

Mrs. Chinmaye R,

Asst.Professor Department of ECE,RVCE

RVCE , Bengaluru

AbstractReversible logic design in recent times has gained interest due to its less heat dissipation and low power consumption .Reversible logic design can be used for realizing any Boolean function using the basic reversible gates. This paper presents the design of T Flip flop and counter using reversible logic gates and comparison of existing reversible T Flip Flop design with optimized reversible T Flip Flop. Asynchronous counters are designed using the existing and proposed T FF. The proposed counter has considerably less power consumption improving the performance of the circuit. Various matrices are tabulated for the circuits designed. Proposed reversible counter is found to be better in terms of power dissipation by about 50% and gate cost by 25% .

Keywords Reversible logic, Low power VLSI, Power dissipation, garbage outputs, constant inputs.

1. INTRODUCTION

   Energy dissipation is one of the main considerations in digital circuit design. The irreversible computation tends to lose information during execution. The information loss dissipates in the form of heat, dissipation of heat results in power dissipation. In order to reduce the power dissipation a new logic called reversible logic has been introduced .The main idea behind this logic is to reduce power dissipation by preserving information content. By implementing circuits using reversible logic a significant amount of heat energy dissipated can be decreased .Due to their capability to reduce power dissipation; it finds applications in low power VLSI design, quantum computation and optical information processing.

   It has been showed that for each bit of irreversible logic computation there will be a loss of kTln2 joules of energy, where k is Boltzmanns constant, t is absolute temperature at which execution is performed [1].Bennet showed there would not be kTln2 energy dissipation if the system allows reproduction of inputs from the produced outputs [2].The main difficulties in designing the reversible circuits are to reduce the number of quantum cost, garbage outputs, delay and constant inputs. This paper proposes optimized design for T flip flop and 4 bit asynchronous counter .

   Reversible T FF designed using Sayem gate is compared with the proposed T flip flop design. Asynchronous counters are designed using both existing and proposed design and compared for power, garbage outputs, transistor cost.

2. REVERSIBLE LOGIC GATES

Reversible logic gates have the same number of inputs and outputs and there is a bijective mapping between inputs and outputs. Any gate is said to be reversible if we can reproduce input vector from output vector and vice versa. Fan out is not allowed in reversible logic, it can be achieved using additional reversible basic gate. This paper discusses about reversible basic gates like Feynman gate, Fredkin gate, Sayem gate and their transistor implementation. These gates are used in implementing sequential circuits.

2. A. FEYNMAN GATE

Figure 1 shows a 2*2 Feynman gate of input vector In(A, B) and output vector Out(P, Q).Table 1 shows the truth table of Feynman gate. The quantum cost of Feynman gate is 1.

The outputs defined as P=A , Q=(A xor B).

This gate can be used for fan out or for duplication of required outputs in reversible circuit design.

Figure 1: Feynman gate Table 1: Truth table

Transistor Implementation:

Figure 2 shows the transistor implementation of 2*2 Feynman gate.

Figure 2: Schematic of Feynman gate.

2. B. FREDKIN GATE

A 3*3 Fredkin gate is as shown in figure 3 with inputsA,BandC and outputsP,QandR. The quantum cost is 5.Table 2 shows the truth table of Fredkin gate whose outputs are defined as

P=A

Q= (AB xor AC) R= (AB xor AC).

Figure 3: Fredkin gate. Table 2: Truth table.

Transistor Implementation:

Figure 4 shows the transistor implementation of 3*3 Fredkin gate. Fredkin gate needs only four transistors.

Figure 4: Schematic of Fredkin gate.

1. C. SAYEM GATE

   A 4*4 Sayem gate is as shown in figure 5with inputs A, B, CandD and outputs P, Q, RandS. The quantum cost of Sayem gate is 14.Table 3 shows the truth table of a 4*4 Sayem gate whose outputs defined as P=A

   Q= (AB xor AC)

   R= (AB xor AC xor D) S= (AB xor AC xor D).

   Figure 5: Sayem gate. Table 3: Truth table.

   Transistor Implementation:

   Figure 6 shows the transistor implementation of 4*4 Sayem gate which is used to design Flip flops.

   Figure 6: Schematic of Sayem gate

2. EXISTING AND PROPOSED DESIGNS OF T FLIP FLOP

3. A. EXISTING REVERSIBLE T FLIP FLOP.

T FF toggles output whenever the input is high and retains the output when input is low. Depending upon the input it either retains the previous state or toggles the output. Table 4 shows the truth table of T FF. Figure 7 shows the implementation of T FF using Sayem and Feynman gates.

Table4: Truth table of T FF

Existing T FF is made up of 2 Sayem gates and 1 Feynman gate. This has 4 constant inputs and 3 garbage outputs.

Figure 7:T-Flip Flop Using Sayem And Feynman Gate(Existing design).

Figure 8 shows the schematic of T flip flop using two Sayem gate and one Feynman gate.

Figure 8: Schematic of existing T flip flop.

1. B. PROPOSED REVERSIBLE T FLIP FLOP.

   Figure 9 shows the design of proposed T FF using basic reversible logic gates. This Flip flop is designed using 2 Fredkin gates and 3 Feynman gates. This Flip flop has 3 garbage outputs and 2 constant inputs. T FF works similar to that of existing reversible T FF.

   T	Qt+1
   0	Qt
   1	Qt

   Figure 9: Proposed T flip flop using basic reversible gates.

   Figure 10 shows the schematic of the proposed T FF.

   Figure 10: Schematic of Proposed T flip flop.

   3.C. ASYNCHRONOUS UP/DOWN COUNTER USING T FLIP FLOP

   The below figure 11 shows a 4 bit asynchronous up/down counter using the reversible T flip flop.The output of each stage is fed to clock of next stage. This has 4 garbage outputs and 4 constant inputs. The proposed T Flip Flop has been used in the design of asynchronous counter instead of existing one.

   Figure 11:4 bit asynchronous up/down counter using proposed reversible T flip flop.

   1. SIMULATION AND RESULTS

      Simulation is based on Cadence Virtuoso ADELtool180nmtechnology. Figure 11 shows the simulation output of reversible T FF .The Flip flop is a negative edge triggered flip flop.

      Figure 12 shows the simulation output of proposed T FF using basic reversible logic gates. The flip flop toggles at negative edge of clock and if T is 1.

      Figure 12 : Simulation of proposed T FF.

      Figure 13 shows the output of a 4 bit asynchronous up/down counter. The counter counts downwards when the up/down signal is high and counts down when up/down control signal is low as shown below.

      Figure 13: Simulation of a 4bit asynchronous counter using proposed T flip flop.

   2. CONCLUSION AND RESULTS

This paper presents the design of basic reversible gates, T flip flops ,asynchronous counters. Comparison of Gate cost, Quantum cost, Power dissipation, Garbage outputs and constant inputs of existing reversibl T FF with the proposed reversible T FF is as shown in Table 5. Also comparison of counters using existing and proposed T flip flops is as shown in Table 6. Proposed reversible T flip flop have considerably less power dissipation than the existing improving the performance of circuits. Hence proposed reversible T flip flop shows a better performance in terms of power and gate cost, quantum cost.

Figure 14 shows the graphical representation of comparison of various metrics of existing and proposed T Flip flops. Figure 15 shows the graphical representation of comparison of power dissipated by existing and proposed T Flip flops.

Figure 16 shows the graphical representation of comparison of various metrics of existing and proposed Asynchronous counters. Figure 17 shows the graphical representation of comparison of power dissipated by existing and proposed Asynchronous counters.

80

60

40

20

0

Table 5: Comparison of existing and proposed T FF.

Existing Proposed

16

14

12

10

8

6

2

4 Existing

0 Proposed

Figure 16: Comparision of metrics for counter design using existing and proposed T flip flops.

Figure 14: Comparision of various metrics of T flip flop.

3.00E-03

2.00E-03

1.00E-03

0.00E+00

Power(W)

Existing

Proposed

6.00E-04

4.00E-04

2.00E-04

0.00E+00

Power(W)

Existing Proposed

Figure 17: Comparison of Power for counters using existing and proposed T FF.

REFRENCES:

1. Landauer, R., "Irreversibility and heat generation in the computing process", IBM 1. Research and Development, 5(3): pp. 183-191, 1961.

2. Bennett, C.H., "Logical reversibility of Computation", IBM J.Research and Development, 17: pp. 525-532, 1973.

3. Thapliyal H, Ranganathan N.," Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs" Centre for VLSI and Embedded System Technologies International Institute of Information Technology, Hyderabad, 500019, India

4. S.K.S. Hari, S. Shroff, S.N. Mohammad, and V. Kamakoti, "Efficient

   Figure 15: Comparison of power consumption of existing and proposed T FF.

   There is 25% reduction in gate cost and 56% reduction in power consumption when compared to the existing design.

   	Gate cost	Quantum cost	Power (W)	Garbage outputs	Constant inputs
   Existing design	31	63	2.11e-3	12	16
   Proposed design	23	55	913.2e-6	12	8

   Table 6: Comparison of counters using existing and proposed T FF.

   building blocks for reversible sequential circuit design," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2006.

5. Abu Sadat Md. Sayem, Masashi Veda "Optimization of reversible sequential circuits" journal of computing, volume 2, issue 6, june 2010, issn 2151-9617

6. Sujata S. Chiwande and Prashanth R. Yelekar, Design of sequential circuit using reversible logic, IEEE-International Conference Advances inEngineering, Science and Management (ICAESM -2012) Marcp0, 31, 2012.

7. M. L. Chuang and C.Y. Wang, Synthesis of reversible sequential elements, ACM journal of Engineering Technologies in Computing Systems (JETC), vol. 3, no. 4, 2008.