A Three Legged DC/DC Converter with Wide and Variable Output Voltage Capability

A Three Legged DC/DC Converter with Wide and Variable Output Voltage Capability

Mr. Aniwas Lama Tamang Dr. K. Shanmukha Sundar

PG Scholar, M.tech (Power electronics) Professor and Head EEE Department, EEE Department,

Dayananda Sagar College of Engg. Dayananda Sagar College of Engg.

Bangalore-78 Bangalore-78

Abstract A new three legged DC/DC converter with reduced circulating current, small output lter, and low conduction loss of the rectier diode for high DC current and a wide DC voltage application is proposed in this paper. It solves drawbacks like large circulating current, large output filter, narrow zero voltage switching range and large duty cycle loss. Two phase shift full bridge (PSFB) are placed on the primary side which works in a phase shifted manner, thus regulating output voltage. A capacitor called a boost capacitor is place to reduce the circulating current. Two full bridge rectifiers sharing two low current rating diodes are placed at the rectifying stage. This proposed converter configuration helps eliminate all the problems of a traditional PSFB converter thus making it suitable for high power applications.

KeywordsPhase shift full bridge (PSFB), Zero voltage switching (ZVS), circulating current.

1. INTRODUCTION

   Zero voltage switching (ZVS) and Zero current switching (ZCS) are the soft switching technique that are used for PWM full bridge converter. The traditional Phase shift full bridge (PSFB) converter discussed in [1] requires no additional active device and utilizes leakage inductance of the power transformer to achieve ZVS. The gating signals are such that, instead of turning on the diagonally opposite switches in the bridge simultaneously, a phase shift is introduced between the switches in the left leg and those in the right leg. The zero voltage turn on is achieved by using the energy stored in the leakage inductance of the transformer to discharge the output capacitance before turning them on. A conventional phase-shift full-bridge (PSFB) converter is an attractive topology for the high- power and wide-output- voltage applications, since it has some desirable features such as low current/voltage stress, the ZVS operation of all primary switches, and variable output regulation capability by the phase- shifted control signal. A full bridge PWM converter permits all switching devices to operate under Zero Voltage Switching (ZVS) by using circuit parasitic to achieve resonant switching. To achieve ZVS, the two legs of the bridge are operated with a phase shift. This operation allows a resonant discharge of the output capacitance of the MOSFETs and subsequently forces the conduction of each MOSFET`s antiparallel diode prior to the conduction of the MOSFET [2].

   The proposed switching control technique [3] controls the full- bridge converter by pulse width modulated (PWM) switching technique under light-load condition and burst

   PWM switching method under standby condition. However, such a converter has several serious problems. The ZVS range of lagging-leg switches is very narrow under load variation. A new PSFB converter with maximum duty operation is proposed in [4]. The proposed converter eliminates freewheeling period by simply replacing the clamp diodes in the conventional converter with MOSFET switches and dividing primary turns into NP1 and NP2. A full-bridge dc/dc converter using a series boost capacitor (SBC) controlled by pulse-frequency modulation (PFM) is proposed in [5]. The proposed converter has a similar circuit conguration to the conventional series resonant converter (SRC). However, it uses a resonance between the magnetizing inductance Lm and the resonant capacitor Cr, whereas the SRC employs a resonance between the leakage inductance Lk and the resonant capacitor Cr. In high-output-voltage applications, a very large output inductor is required to reduce the large ripple current, which results in low power density and high cost [5].

   In converter present in [6], it has advantages of the incorporating a saturable resonant inductor. The size of the saturable inductor is very small since magnetic material with very high permeability can be employed. However using a saturable reactor on the primary side to increase the ZVS range increase the amount of heat generated in the reactor thus making it bulky [7]. In converter presented in

   [8] and [9] it uses an auxiliary transformer winding to the ZVS PWM full-bridge converter to be in series with the resonant inductance. The introduced winding not only makes the clamping diode current decay rapidly and reduces the primary side conduction losses, but also can makes the current ripple of the output lter be smaller; hence the output lter capacitor can be reduced. Even though with all the said modifications it still has the drawback of a large output inductor when used for high output voltage applications and the current stress on all the switches is higher than the traditional PSFB converter due to the assistance of current source for a wide ZVS range which may even lead to increased conduction losses [10] – [14]. In paper presented in [15], [16] an improved current- doubler rectier with coupled inductors is proposed. In comparison with the conventional current-doubler rectier (CCDR) the component counts of the proposed rectier are identical, while the proposed rectier can adjust the turns ratio of the coupled inductor to extend the duty ratio range,

   which can reduce the peak current through the isolation transformer and switches and can lower output current ripple. A ZVS and soft-commutating two transformer full- bridge PWM converter using the voltage ripple is proposed as shown in [17]. In the proposed converter, the ZVS operation of lagging leg is achieved along the whole load range using the energy stored in the magnetizing inductor of transformers. In PSFB converter with series-connected two transformers however due to the use of two transformers, the ZVS operation in the converters is achieved under entire load conditions. However, for ZCS operation and counter measures to side effects such as high secondary-voltage stress and primary-current overshoot, they require many additional components, which results in high cost and a complex structure [18], [19].

   The active clamp method [20]-[23] can solve the efciency degradation problem and the voltage overshoot can be clamped, but it increases system complexity and degrades system reliability. A novel Energy Recovery Clamp Circuit (ERCC) employs a simple auxiliary circuit in which neither lossy components nor active switches are used. Therefore, the efciency and reliability of the dcdc converter can be improved with this ERCC. But using IGBTs to suit ZCS operation precludes the use of high switching frequency to realize smaller magnetic components and capacitors. Also, its large output inductor in high-voltage applications is an additional drawback.

   PSFB converters with the ZVS capability in a wide load range and reduced output lter was presented in [24]. It is well suited for applications in the range of a few hundred watts to a few kilowatts. It is essentially a hybrid combination of an uncontrolled half-bridge section and a phase-shift controlled full-bridge section, realized with just four switches. The main features of the proposed topology are zero-voltage-switching down to no-load without serious conduction loss penalty, constant frequency operation and near-ideal filter waveforms. The improved filter waveforms result in significant savings in the input and output filter requirement, resulting in high power-density. The new topology requires two transformers and two dc-ypass capacitors. The combined VA rating of the two transformers is more than that of the single transformer of conventional full-bridge converters, for variable-input applications. But the primary circulating current is still in the controlled full-bridge inverter. The PSFB converter designed for server power system can always operate with a maximum duty cycle under all line conditions. This operation minimizes the circulating current and reduces the lter requirement. Yet, two additional main switches in the primary side increase the cost and circuit complexity.

   If the converter presented in [25] is to be modified than we can achieve its implementations on various applications. The existing circuit topology has few drawbacks when used for applications that require output voltage variation like primary conduction losses, large circulating current exists on the primary side during the freewheeling period. Beside, the size of the output filter is highly increased due to small

   duty operation and it results in low power density and high cost.

2. DESCRIPTION OF THE PROPOSED CIRCUIT

   The circuit diagram of the proposed converter. As shown in Fig. 1, the proposed converter is composed of two Phase Shift Full Bridge converters PSFB1 and PSFB2 that are placed in parallel on the primary side. One of PSFB converters PSFB1 consists of switches S1, S2, S3, S4 and a transformer T1. The other converter PSFB2 consists of switches S2, S4, S5, S6, a small capacitor, CB and a transformer T2. Both PSFB converters share switches S2 and S4. In order to eliminate the circulating current of T2, CB is connected in series with T2 as shown in Fig. 1.4. Due to the voltage across this capacitor, which is called the boost capacitor, the circulating current of T2 is reset during the freewheeling period. In the secondary side, both main transformers T1 and T2 are connected in series and a full- bridge rectier consisting of D1, D2, D3, D4 and low voltage diodes DL1 and DL2.

   OPERATING PRINCIPLE

   In order to illustrate the operation of the proposed converter, several assumptions are made:

   1. All switches are ideal except for output capacitor, Coss and the internal antiparallel diode of it.

   2. The output inductor LO is large enough to be

      considered as a constant current source during a switching period.

   3. The blocking capacitor CB is large enough to be considered as a constant voltage source of VIN/2.

   4. The output capacitor CO is large enough to be considered as a constant voltage source of V0.

   5. The magnetizing inductance Lm2 of the transformer T2 is large enough to ignore the effect of the magnetizing current during a switching period.

   6. The main switches are all MOSFETs with parasitic diodes of Db1, Db2, Db3 and Db4.

   7. The output capacitances of all MOSFETs have the same capacitance of COSS

   8. The transformers of T1 and T2 have the same turns ratio of n = NS1/NP1= NS2/NP2

The switching period is in 2 half cycles i.e., (t0-t8) and (t8- t16). Due to the symmetrical operation of the converter only one half cycle is discussed.

Mode 1 (to to t1):- Switches S1, S2 and S5 are ON in this mode and the remaining switches are OFF. During this mode, positive input voltage Vs is applied to the primary voltage vpri1(t) of T1 i.e., Vs = vpri1(t) and – (Vs vCb(t)) is applied to the primary voltage vpri2(t) of T2.vpri2(t)

= – (Vs vCb(t)). Since ipri2(t) charges the boost capacitor CB, the voltage v cb (t) of CB is linearly increased in this mode. The energy stored in transformers T1 and T2 is transferred to the output through D1 and D2. The output voltage of rectier stage vrec(t) is the sum of reected voltage vsec1(t) of T1 and reected voltage vsec2(t) of T2.

Vrec = n (Vs 0.5 VCB)

Mode 2 (t1 to t2):- At time t1, S5 is turned OFF.

inductor LlK1 of T1 and leakage inductor Llk2 of T2 so that ipri1(t) and ipri2(t) are rapidly decreased to the negative side.

The output capacitors Coss of switches S5 and S6 are linearly charged and discharged, respectively, by the energy stored in the output inductor Lo. vpri2(t) is linearly decreased to zero and the primary vpri1(t) is continuously maintained at Vs.

ipr1 ipr2

= – 1

1

= – 2

2

Mode 8 (t7 to t8):-At this time, since the

vpri2(t) = 0

vpri1(t) = Vs. Hence, vsec2(t) is decreased to zero voltage.

Mode 3 (t2 to t3):-Switch S6 is turned ON. vpri1(t) is still maintained at Vs during this mode. Hence, vrec(t) is maintained at 0.5nVs and ipri1(t) is continuously increased. During mode 3, since the commutation between D2 and D6 is progressed, total vB(t) is applied to Llk2 and ipri2(t) starts to decrease rapidly.

vpri1(t) = Vs vrec(t) = 0.5nVs

Vb = (1/CB) Ipri2

Mode 4 (t3 to t4):- When the commutation between D2 and D6 is completed, mode 4 begins. Since ipri2(t) is in the zero state, the input power is transferred to the output stage through only T1,D1 and D6.The voltage of boost capacitor vB(t) remains its maximum value and the secondary voltage vsec2(t) of T2 is decreased.

Vb = (1/CB) Ipri2

Mode 5 (t4 to t5):-At time t4, S1 and S2 are turned OFF and mode 6 begins. Since vsec1(t) remains in the positive side. The output current still ows through T1, D1 and D6 during this mode. Hence, Coss of S1, S2, S3 and S4 are linearly charged and discharged, respectively.

Mode 6 (t5 to t6):-When the sum of vsec2(t) and vsec1(t) reaches at zero voltage, mode 6 starts. At time t5, D4 starts to conduct and the commutation between D1 and D4 is progressed. The Coss of S1, S2, S3 and S4 is charged and discharged, respectively.

commutation between D3 and D6 is progressed, Vs is applied to the Llk1 and ipri1(t) is continuously decreased to the negative side. The negative

Fig 1:- Circuit diagram of the proposed converter

Fig 3:- Mode 1 (to to t1)

Z = 1+2 and w = 1

o 4 0 4 1+2

ipr1 = 1 Zo cos(wo) ipr2 = -Zo cos (wo) Vp1 = 2ipr1 Zo sin(wo) Vp2 = 2ipr1 Zo sin(wo)

Mode 7 (t6 to t7):- After vpri2(t) and vpri1(t) reach

Vs, the antiparallel diode of S3 and antiparallel diode of S4 start to conduct. The ZVS operation of S3 and S4 is achieved. During this mode, the commutation between D1 and D4 is still progressed. The sum of the input voltage Vs and divided voltage of VB is applied to both leakage

Fig 5:- Mode 3 (t2 to t3)

Fig 7:- Mode 5 (t4 to t5)

Fig 2: – Key operating waveform during various mode.

Fig 4:- Mode 2 (t1 to t2)

Fig 8:- Mode 6 (t5 to t6)

Fig 9:- Mode 7 (t6 to t7)

Fig 10:- Mode 8 (t7 to t8)

voltage Vs + vB(t) is applied to vpri2(t).The input energy is transferred to the output through T2, S4, S6, D6 and D4.

ipr1

= –

1

Fig 6:- Mode 4 (t3 to t4)

ipr2 = – 0.5nIo vpr1= – Vs + vB

1. DESIGN CONSIDERATION

   1. Choose Dmax. Dmax should be chosen as large values as possible in order to maximize (NP/NS) and for the reduction of conduction losses.

   2. Choose Vsec. The minimum value should be chosen to maximize (NP/NS). When (NP/NS)is increased, it reduces the primary current and increasing the leakage inductor value. The initial choice of Vsec is somewhat arbitrary and the final value is obtained after several iteration. Vsec should satisfy,

2. SIMULATION:-

The figure below shows the circuit arrangement of fig 1 in MATLAB simulation package. The performance of the proposed converter is verified for the input DC voltage of 350 V and the dc output of 205 V is obtained.

Vsec

1. Voltage Conversion Ratio:- The voltage

   conversion ratio of the proposed converter without considering the effect of boost capacitor can be expressed by averaging the rectifier output voltage.

   M = = (D + 0.5) n

   The voltage conversion ratio of the proposed convertr at dual full-bridge mode without considering the effect of the boost capacitor is the same as that of the circuit in [24]. However, when considering the effect of the boost capacitor, the turns ratio of transformer T2 can be slightly changed. The voltage conversion ratio of the proposed converter can be slightly increased and turns ratio of transformer T2 can be designed as a smaller value [26].

   Fig 11: Circuit Arrangement in MATLAB Simulation Package

   SPECIFICATION

   CB

   4

   PARAMETERS	VALUES
   Input DC Voltage	350V
   Switching Frequency	100 KHz
   Output Power, Po	1025W
   Output Inductor, Lo	26.5 µH
   Output Capacitor, Co	300 µF
   CB	500 nF
   Llk1	0.0043 µH
   Llk2	0.00226 µH
   LM1	302 µH
   LM2	407 µH

2. A full-bridge rectier is employed on the

   secondary side. However, due to the oscillation of parasitic circuit elements the rectier diodes still suffer from high voltage stress. Therefore, a high-voltage-rated diode has to be used for the rectier stage. In the rectier stage of the proposed converter, the diodes D5 and D6 are placed at the midpoint of both transformers T1 and T2 with a full-bridge rectier.

3. The magnetizing inductor Lm1 of T1 is designed as a small value, increased magnetizing current can increase the conduction loss of primary components, the effect of magnetizing current on primary RMS current is negligible at heavy load condition as already discussed in

   [25] and the leakage inductor is given by.

   2

   1 2()2 1.33 0.5 2

4. The voltage across the output inductor is given by (nVs-Vo) (Vo/nVs 0.5) and the change of the converter that is flowing through the inductor is ILo. The value of the output inductor filter is given by,

Fig 12:- Component lists

SIMULATION RESULTS

The simulation of the proposed converter was verified using MATLAB-SIMULINK, a simulation software widely used. The simulations shown below represent the various quantities as mentioned below.

Fig. 13:- Primary current of transformer T1 and transformer T2. Scale: X-axis:- Time (Each division = 0.00001 sec)Y-axis:-

L = (

0.5) 1

Magnitude (Each Block = 2 A)

o

The primary current of transformer T1 and transformer T2 are denoted by solid and dotted lines respectively, as shown above. Mode 1 results in increase of the transformer T1 primary voltage, likewise the primary current of transformer T1 increases till mode 5 and then decreases till mode 8 and then the symmetric operations occurs thereafter, while the primary current of transformer T2 increases in negative side and as the voltage across primary of the transformer T2 goes to positive side, the current also becomes positive.

Fig. 14:- Primary transformer voltage of T1 and T2

Scale:X-axis:- Time (1 division= 0.00001), Y-axis:-Magnitude (Each Block= 100 V)

The primary voltage of transformer T1 and transformer T2 are denoted by solid and dotted lines respectively, as shown above. The figure above shows the waveform of primary transformer voltage of T1 and T2. As we have already discussed the waveform of primary current to transformer T2, so as long as the current in the primary winding of the transformer T2 is positive, the voltage across it is also positive. Likewise, when the current in the primary winding of the transformer T2 is negative it is seen the voltage of the transformer also to be negative. Same goes with transformer T1.

Fig 15:-Waveform of secondary voltages of the transformers

Scale: X-axis:- Time (Each division=0.00001 sec) Y-axis:- Magnitude (Each Block= 50 V)

The waveform shown above is the waveform of secondary voltage of transformer T1 and transformer T2 The secondary voltage of transformer T1 and transformer T2 are represented by Solid and Dotted lines respectively, as

shown above in the figure. As long as the voltage across the transformer T1 and transformer T2 remains positive values the secondary voltage also remains positive and the same happens when the voltage of the transformers goes to its negative value. Maximum value of secondary voltage of transformer T1 and transformer T2 is nVs i.e., 154 Volts.

Fig 16:-Waveform of output voltage.

Scale: X-axis:- Time (Each division=0.002 sec) Y-axis:- Magnitude (Each Block= 50 V)

The figure above shows the simulation results of output voltage of the proposed converter for the input DC voltage of 350 V. The output voltage is 205 V. Similarly the output current waveform is shown below with the same value of load. The current obtained is 5 A direct current.

Fig 17:-Waveform of output current.

Scale- X axis:-Time (Each division=0.005 sec) Y-axis:- Magnitude (Each Block= 2 A)

APPLICATIONS

• Used in hybrid vehicle system that use high voltage starter/generator.

• Used in Telephone exchange communication.

• Used in street LED lightening, 48V.

• Used in SMPS power supplies for Desktop, LED TV, LCD displays.

• Used in Industrial control and Process control instrument set up.

• Used in telecom applications 230V/48V.

• Used in high power applications and various applications that uses high DC current and DC voltage.

CONCLUSION

A new three legged DC/DC converter with reduced circulating current, small output lter, and low conduction loss of the rectier diode for high DC current and a wide DC voltage application is proposed. Connecting a capacitor in series with one transformer T2, it is seen that the circulating current is greatly reduced. The ZVS operation of all switches is well achieved even though the circulating current is reduced. The waveform of the rectier output voltage is improved with size reduction of the output inductor. Since the load current is distributed to the additional low voltage rated diode, the reduction in the secondary conduction loss in the proposed topology is seen. With all these advantages, it results greatly in improvement of efciency over wide output voltage. Therefore, the proposed converter has advantages and is suitable for a wide output voltage applications as mentioned earlier.

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