Simulation of a Software Phase-Locked Loop for Typical Grid Disturbances

Simulation of a Software Phase-Locked Loop for Typical Grid Disturbances

Rueda-Germán Clementina1, Rivas- Cambero Ivan1, Arroyo-Núñez J. Humberto1

1Electronic Engineering Department Universidad Politécnica de Tulancingo Tulancingo Hidalgo, México

Abstract During the last year various techniques of electrical synchrony have been proposed for the interconnection of local power generation systems of small scale with the national electrical grid. This paper presents the simulation of second-grade software Phase-Locked Loop (PLL), to analyze the state of engagement (phase tracking) when the reference signal has disturbances.

KeywordsSPLL, Phase Locked Loop, Loop Filter (LF), grid disturbances.

1. INTRODUCTION

   Most applications of local systems for power generation (LSG) connected to the utility power grid require synchronization between the grid voltage and the voltage synthesized by the converter.

   In many cases, the reference signal obtained from the grid voltage is contaminated by harmonics, which may have been produced by the power converter itself or generated elsewhere [1].

   The most widely accepted solution to provide synchronization between time-varying signals is the use of a Phase-Locked Loop (PLL) system [8]. A PLL is a device which causes one signal to track another one. It keeps output signal synchronization with a reference input signal in frequency as well as in phase [ 2].

   Every type of PLL (lineal PLL (LPLL), digital PLL, etc.), can be implemented by software (SPLL) [3].The design of a SPLL (Software-PLL) is similar to analog PLL, The advantage of such a software implemented is that the loop could be easily modified to incorporate signal processing components to improve the performances of the PLL [4].The block diagram of SPLL is given in Fig. 1, the first block is Analog Digital Converter (ADC), the phase detector is a multiplier (MUL), a proportional Integral controller (PI) is the loop filter, and in the last block a Digital Controller Oscillator (DCO) is located in the last block [5].

   Fig. 1 Block diagram of SPLL

   The goal of this work is to analyze the performance in phase tracking of a software-based lineal PLL (SLPLL) second-degree, when a reference electrical signal has normal and abnormal conditions. The SLPLL is tuned to work with the Mexican Electrical System (MES) 60 Hz of operation frequency.

   The organization of the paper is as follow: in the next section the PLL components are studied, the second-order PLL structure is discussed in the subsequent stage, in the last three sections; filter design and simulation, second-order PLL simulation and results are presented.

2. PLL COMPONENTS

   A phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal [6]. Fig. 2 shows the basic model for a PLL. The basic blocks of the PLL are the Error Detector (composed of a phase frequency detector), Loop Pass Filter (LPF), and VCO.

   Fig. 2 Lineal basic model of the phase-locked loop [ 2]

   1. Phase Detector (PD)

      A phase detector is a device capable of generating a signal which is proportional to the phase difference between two signals, a multiplier is used usually [7].

   2. Loop Filter

      The next stage after the phase detector is the loop filter. The loop filter aim is to do stable the PLL, filtering the unwanted high frequencies. The PLL acts as a low pass, eliminating noise and spurious signals input and as a high pass to VCO noise [8].

   3. Voltage controlled oscillator (VCO)

   The VCO operates at a set frequency. If the frequency of the reference signal is near to the VCO frequency, the PLL feedback causes the VCO is engaged with the input signal. The VCO input is a voltage and the output is a frequency. [9].

3. SECOND-ORDER PLL DESCRIPTION

   The second-order PLL system contains a first-order filter and a voltage controlled oscillator (VCO) [10]. The transfer function of an analog loop filter (1) and a VCO (2) are [10]:

   A. Matlab® Filter simulation

   (11)

   (1)

   (2)

   Where F(s) and N(s) are the transfer functions of the filter and VCO. Ko is the VCO gain. The transfer of a linearized analog PLL is [11] (3).

   (3)

   is the PD gain. Substituting Equations (1) and (2) in

   (3) yields (4)

   (4)

   Where the natural , and the damping ratio [10]. The damping ratio controls how fast the filter reaches its settle point, also controls how much overshoot the filter can have. The damping is chosen to = 0.7 resulting in a filter that converges reasonably fast [[10].

   The transfer function (4) is analog version and to convert the transform function to digital form; for future implementation in a DSP, the bilinear z transformation is used; this yields the following digital transfer functions for the PLL model (5).

   Matlab is used as a tool for simulating the PI filter algorithm. The choice of Matlab as programming and simulation environment was for the simplicity of use and the ability to integrate systems.

   The technical specifications for the simulation of the algorithm are:

   • Reference signal sinusoidal frequency 60 Hz. and amplitude 1 V.

   • Sampling frequency 8000 Hz.

   • DCO center frequency 60 Hz (376.9911 rad/s).

   • PLL lock range 59.5 Hz to 60.5 Hz. operating frequencies required by the Comisión Federal de Electricidad (CFE) parastatal that manages the supply of electricity in México.

   The simulated filter is analog type with amplification near to 60 Hz frequency to improve the performance of closed loop and the PLL lock range.

   The filter coefficients are calculated according to (8), (9),

   (10) and (11), and substituted in (7), obtaining the following values:

   a0= 1,

   a1= -0.9612,

   b1= -0.2869,

   b2= 0.3256.

   The filter response is shown in Fig. 3. The figure shows attenuation in the frequency close to 60 Hz (376.9911 rad/s).

   (5 0

   ) -2

   Bode Diagram

   System: sys Frequency (rad/s): 367

   Magnitude (dB): -3.16

   Magnitude (dB)

   In-lock state, the output of the phase detector can be -4

   approximated as (6) -6

   (6)

   -8

   -10

4. FILTER DESIGN AND SIMULATION

An active filter PI offers a good performance of a SPLL [12], it is assumed that (1) is the transfer function of an active filter PI in digital form, obtained through bilinear transformation (7).

(7)

The filter coefficients are given by (8), (9), (10) and (11):

(8)

(9)

(10)

-12

0

Phase (deg)

-10

-20

-30

-40

0 1

10 10

2 3 4 5

10 10 10 10

Frequency (rad/s)

Fig. 3 Filter response

1. SECOND-ORDER PLL SIMULATION

   The algorithm in Fig. 4, describes the SPLL process, begins with the initialization of the relevant variables, once the variables are initialized the algorithm enters an infinite loop and the instructions are executed repeatedly until the system is paused or turned off. Walsh function is implemented in subsequent lines and the values of all variables are updated, the next step is set back all the variables values (or displace in time) [7].

   2

   1.5

   1

   Amplitude(V)

   0.5

   0

   -0.5

   -1

   -1.5

   -2

   Reference signal

   0 0.02 0.04 0.06 0.08 0.1 0.12 0.14

   t(s)

   Fig. 6 Reference signal

   2

   1.5

   <>1

   Amplitude(V)

   0.5

   0

   -0.5

   -1

   Fig. 4 Algorithm based on a PLL used for tuning radio frequency [12]

   Fragment of program code [13] developed by Matlab®

   -1.5

   -2

   0 0.02 0.04 0.06 0.08 0.1 0.12 0.14

   Time(s)

   shown in Fig. 5.

   Fig. 5 Fragment of SPLL program code

   In order to test the performance of the algorithm SPLL, a number of changes to the reference signal, similar to the characteristic disturbances of the mains are made.

   1. System response with an ideally stable input

      The electrical single phase signal should have a 60 Hz oscillation frequency, as shown in Fig. 6. This simulated signal is a reference for the SPLL to produce a square signal (sync pulse) with the same phase characteristics, sync pulse and the reference signal in Fig. 7 is shown, noting that they are in perfect synchrony.

      Fig. 7. Reference signal (sinusoidal wave) and sync pulse (square wave)

   2. Disturbances in the reference signal

      The transient stability of a power system can be defined as the system's ability to stay in sync when it experiences the occurrence of a severe disturbance [14] the aim of the researches on the transient stability is to determine the dynamic response of the system, during and after the occurrence of a great disturbance [15]. The disturbances such as short circuits, sudden loss of large amounts of electrical loads, own generation loss, loss of interconnection with the distribution network, network failures nearby power transmission interconnection point, are classified according to their magnitude in [15]:

      • Small-scale disturbances: They are caused by normal variations in the system load and loss of small generators.

   • Large-scale or severe disturbances: loss of large generators and short circuits in the transmission line.

2. RESULTS

   In this section SPLL performance is shown with different reference signals modified according the main MES disturbances.

   1. 180° phase change

      A phase change of 180 ° is applied in the reference signal in Fig. 8.

      3

      2.5

      Amplitude

      2

      1.5

      1

      0.5

      0

      4

      Harmonic

      0 50 100 150 200 250 300 350 400 450 500

      Hz

      2

      1.5

      1

      Amplitude (V)

      0.5

      0

      Reference input signal

      2.5

      2

      amplitude

      0

      -2

      -4

      0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

      t(ms)

      Fig. 10 Harmonics in the reference signal

      -0.5

      -1

      -1.5

      2

      1.5

      1

      -2

      0 0.02 0.04 0.06 0.08 0.1 0.12 0.14

      Time (s)

      0.5

      amplitude

      0

      Fig. 8 Reference signal 60 Hz frequency, 180 ° phase.

      Fig. 10 shows the reference signal and the synchronized pulse achieved even when the reference signal has a phase shift.

      2

      -0.5

      -1

      -1.5

      -2

      -2.5

      0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

      t(s)

      1.5

      1

      Amplitude (V)

      0.5

      0

      -0.5

      -1

      -1.5

      -2

      0 0.02 0.04 0.06 0.08 0.1 0.12 0.14

      Time (s)

      Fig. 11 System Response (green wave) to a reference signal with 3rd, 5th and 7th harmonic (blue wave)

      C. Electromagnetic transients

      It is called transient to the event which is undesirable and momentary. [17].

      Impulse transient. It is a sudden change in the steady state condition of voltage and / or current is unidirectional with positive or negative polarity. In Fig. 12 the response of the PLL to a reference signal with abnormal conditions is observed.

      Fig. 9 Pulse in sync with a phase 180° shift reference signal

   2. Harmonic analysis

   Harmonics are currents and / or voltages present on an electrical system, are signals with a multiple frequency of the fundamental frequency [16]. MES has an operating frequency of 60 Hz and single phase loads that generate harmonic: the third harmonic operating at 180 Hz, 300 Hz fifth and seventh 420 Hz.

   The reference signal; which is shown in Fig. 10, contains the type of harmonic described in the previous paragraph; this signal is used to check the second-order PLL level tracking the generated sync signal and the reference signal are reported in Fig. 11.

   Fig. 12 PLL responses to a transient impulse.

3. CONCLUSION

In this paper a simulation of a second-order SPLL has been presented with the aim of analyzing the performance in tracking phase of a disturbance reference signal.

The results demonstrate that the pulse generated by the PLL is able to track in phase with the reference signal. The technical characteristics of the reference signal were modified, in order to test the phase monitoring, obtaining a fast and efficient response allowing synchrony between the two signals.

Common electrical disturbances grid was used to generate changes in the reference signal and test the second-order PLL lock ability. The evidence shows that the proposed system is able to produce a sync signal in phase with the reference signal.

REFERENCES

[1] Rolim, l. G. B., Costa jr, d. R., & Aredes, m. (2003). Analysis and software implementation of a robust synchronizing PLL circuit. In IEEE International Symposium on Industrial Electronics (ISIE).J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2. Oxford: Clarendon, 1892, pp.68-73.

[ 2] Hsieh, G. C., & Hung, J. C. (1996). Phase-locked loop techniques. A survey. Industrial Electronics, IEEE Transactions on, 43(6), 609-615..

1. Lopez, J., Sandoval, F., & Santana, J. Implementación de un PLL Digital con Dispositivos programables en VHDL. Ele, 24, 1.

2. Sithamparanathan, K. (2006). A software phase locked loop from theory to practice: TMS320C6000 DSP based implementation and analysis. In AusWireless conference 2006 (pp. 1-6). University of Technology, Sydney.

3. Rueda Clementina, Arroyo Humberto, Rivas Iván. Implementation of an embedded phase and frequency tuner, as reference for real-time energy exchange with the grid. Sixth International in Symposiym on Energy & Technology Innovation Forum, Puerto Rico, 2014.

4. VCO, E. D. L. F., & Divider, F. Fundamentals of Phase Locked Loops (PLLs).

5. Bibyk, S. (1998). A Digital Frequency Synthesizer Using Phase Locked Loop Technique (Doctoral dissertation, The Ohio State University).

6. L.A. Bulus, J. M. Juárez, H.E. Lorente Sintetizador de frecuencia PLL controlado por DDS, en XII Reunión de trabajo de Procesamiento de la información y control, Río Gallegos, Argentina, 2007

7. Tomasi, W. (2003). Sistemas de comunicaciones electrónicas. Pearson educación.

8. Borre, K., Akos, D. M., Bertelsen, N., Rinder, P., & Jensen, S. H. (2007). A software-defined GPS and Galileo receiver: a single- frequency approach. Springer Science & Business Media.

9. Chung, B.-Y., Chien, C., Samueli, H. & Jain, R. (1993). Performance analysis of an all-digital BPSK direct-sequence spread-spectrum IF receiver architecture. IEEE Journal on Selected Areas in Communications, 11(7):10961107.

10. E.Best, R. (2007). Phase-Locked Loops, design, simulation, and applications . In R. E.Best, Phase-Locked Loops, design, simulation, and applications (pp. 6-7). Zurich: McGraw-Hill Professional; 6 edition

11. Ummethala, Upendra., Mellor Mike. Software Linear PLL MATLAB design and simulation program

12. Kundur P. Power System Stability and Control. Mc Graw Hill. 1994.

13. Calderon-Guizar, J.G.. Estudios de estabilidad transitoria en sistemas eléctricos industriales con generación propia interconectados con el sistema de transmisión. Ing. invest. y tecnol. [online]. 2010, vol.11, n.4, pp. 445-451. ISSN 1405-7743.

14. Tejada, A., & Llamas, A. (2010). Efectos de las armónicas en los sistemas eléctricos. Recuperad:(7 de noviembre del 2011) http://www. mty.itesm.mx/decic/deptos/ie/profesores/allamas/cursos/ueee/armonica s/07E fectarm. PDF.

15. Sarmiento Jadán, F., & Sánchez Calle, V. (2009). Análisis de la calidad de la energía eléctrica y estudio de carga de la Universidad Politécnica Salesiana Sede Cuenca (Doctoral dissertation).