Design of a Low Power Current Steering Digital to Analog Converter in CMOS

Design of a Low Power Current Steering Digital to Analog Converter in CMOS

Ranjan Kumar Mahapatro

1. Tech, Dept. of ECE

   Centurion University of Technology & Management Paralakhemundi, India

   Sandipan Pine

   Professor, Dept. of ECE

   Centurion University of Technology & Management Paralakhemundi, India

   Abstract In this paper it deals with the design & analysis of a 16-bit current steering digital-to-analog converter. The digital-to-analog converter contained eight sets of current mirrors with different weight. The digital-to-analog converter was implemented using GDI Technology (Gate Diffusion Input) in CMOS process. The average INL and DNL are 0.27 LSB and 0.32 LSB, respectively. At the sample rate of 350 MHz and supply voltage of 3.5 V, the DAC consumed about 66.903 nW. The SFDR was -37 dB. The digital-to-analog converter of this construction consumed less power and chip area. It is suitable for portable device application. . The proposed circuit design simulation can be done using NI- Multisim 13.0 software.

   Keywords: – DAC, SDFR, INL, DNL

   1. INTRODUCTION

      Our world is not a digital environment of absolutes. The signals of the real world are not made of logical highs and lows, or zeroes and ones. These signals are analog and they meander within a range of voltages or currents. The purpose of the Digital to Analog Converter (DAC) is to convert digital data into an analog signal where the real world exists. The digital data may originate from a microprocessor, ASIC, or FPGA, but at some point it requires conversion to an analog signal to have impact on the real world. Whether the system uses an audio amplifier, or an LED indicator, or a motor driver, the final signal will be analog in nature. The DAC serves as that bridge to transfer a digital signal into the analog domain and hopefully ends with an accurate output signal.

      In recent years, the current steering converter is the dominant construction for very high speed Digital to Analog Converters (DAC). The current steering DAC has the advantages of being quite small for resolution below 14 bits, being very fast, and being more cost effective. However, the major drawback is its sensitivity to device mismatch, glitches, and current source output impedance for higher number of bits. For example, its integral non-linearity (INL) and differential non-linearity (DNL) are vulnerable to the accuracy of current sources. Generally, a self-calibrated circuit can be designed to solve these problems, but the circuit will consume more power and require a large chip area.

      Current steering DAC has three main designs: Binary Weighted Current Steering DAC Thermometer Coded Current Steering DAC and Segmented Current Steering DAC. In a binary implementation, one bit in the digital input word directly turns a relative current source on or off, and the output sums up all the current sources that are turned on. The current value is proportional to the input binary word. The binary structure is simple and requires less area and less power, as no decoding logic is required. However, its major drawback is its down-graded performance mainly due to glitches at middle code transitions and stringent matching requirement of the current sources.

      For example, when the digital input code changes from 0111. . .1 to 1000. . .0, one MSB turn on and all the other LSBs turn off. Glitch will be induced during the switching of input code. It is a limitation of high-speed operation of DAC. Although the die size of a binary weighted converter might be relatively small, its specifications for dynamic performance are stringent. Therefore binary weighting is not suitable for high-speed digital-to-analog conversion.

      The thermometer-coded DAC, also called unary DAC, utilizes a number of equally weighted elements. Thermometer-coded DAC is invariably monotonic. When the digital input increases by 1 LSB, one current source is switched from negative to positive, and the analog output always increases with input signal. In comparison, the binary- weighted type manifests poorer dynamic performance than the thermometer-coded type. For a large number of bits, the digital circuits converting the binary code into thermometer code and the number of interconnecting wires become large. This implies a more complex circuit layout. Therefore, the disadvantages of the thermometer-coded DAC are its complexity, consumption of a large area and the larger power requirement of the binary-to thermometer decoders.

      The segmented current steering is a very popular approach for designing digital-to-analog converters because it combines the advantages of binary-weighted and thermometer-coded designs. The segmented DAC is commonly to use a thermometer-coded approach for the top few MSBs while using a binary-weighted approach for the

      lower LSBs. In this way, the glitch is significantly reduced and accuracy is high for the MSBs. Subsequently, the circuit area is minimized with the segmented DAC (Fig. 1).

   2. CONSTRUCTION

      There were four thermometric configurations of (S2 S1 S0), namely (111), (011) (001) and (000). For example, if (S2 S1 S0) = (011), then I1 was the total current drawn by M2 and M3. The relationship between I0 and I1was derived as follows:

      L

      W L

      The proposed differential mode DAC was formed by two

      I I

      M 0 S1 S 0 S1 S1 S 0 Iunit

      (1)

      single-ended DAC circuits. The single-ended DAC contained binary-to-thermometer (BT) decoders and current mirror circuits, as shown in Fig. 4. The current mirror circuit contained eight current mirrors of different weighting. Each current mirror is controlled by a 2-bit binary to thermometer code decoder, as shown in Fig. 2. The proposed DAC has the advantage of low chip area. It is owing to low transistor count of this construction. The MOS transistor has larger capacitances in its gate oxide, source and drain. Moreover, less number of transistors has the possibility of less interconnection than those of more transistors. Dynamic power consumption of MOS circuits is proportional to the total capacitances of load and internal node. Low transistor count DAC has the chance for low total capacitances. Therefore, the proposed DAC has more possibility to consume low power.

      0 1 W

      M 1

      Where Iunit was the unit output current of the 2-bit DAC when (S2 S1 S0) = (001). The operators , were the Boolean AND, and Boolean OR, respectively. The I1, shown in Fig.3, was determined by the parallel resistance of M2, M3 and M4

      Fig. 2 Two-Bit BT decoder.

      Fig. 1. Single-ended DAC construction

      1. Binary to thermometer (BT) decoder

         Fig. 2 shows the constitution circuit of one 2-bit binary to thermometer decoder. It consisted of one AND gate and one OR gate. S0, S1, and S2 were the control signals for current mirrors. The 16-bit DAC decoder of differential mode required only eight AND gates and eight OR gates.

      2. Current mirror construction

      Fig. 4 shows a single-ended 16-bit DAC. It contained eight BT decoders and eight current mirrors. Each current mirror generated 2-bit DAC.

      Fig. 3 depicts the circuit of one 2-bit DAC. The three

      Fig. 3 Current mirror circuits of 2-bit DAC

      The current mirrors of the 16-bit single-sided DAC needed 24 NMOS transistors as switches to turn the current on or off. Iout collected all the current from current mirrors.

      The output Iout can be described as follows:

      Iout = [(B1 B0) + (B1) + (B1 B0)] (Iunit)

      + [(B3 B2) + (B3) + (B3 B2)] (4 Iunit)/p>

      NMOS transistors, M2M4, were switches that turned on the current path. The three signals, S0S2, were generated by the

      + [(B5 B4) + (B5) + (B5 B4)] (16 I

      unit)

      previous BT decoder stage. I0 were the drain current of M0 mirrored from I1, the drain current of M1. Transistors M2, M3 and M4 acted as switches. When they were turned on, effective resistance appeared between the drain of M1 and ground. For example, when the switch was turned on via S0, the effective resistance of M2 appeared between the drain of M1and the ground.

      + [(B7 B6) + (B7) + (B7 B6)] (64 Iunit)

      + [(B9 B8) + (B9) + (B9 B8)] (265 Iunit)

      + [(B11 B12) + (B11) + (B11 B12)] (1024 Iunit)

      + [(B14 B13) + (B14) + (B14 B13)] (4096 Iunit)

      + [(B16 B15) + (B16) + (B16 B15)] (16384 Iunit)

      For example, Iout = 3 Iunit for (B1 B0)2 = (11)2, and Iout = Iunit for (B1 B0)2= (01)2.

      In Fig. 3, the PMOS transistors M0 and M1 were used as a basic current mirror. The width of the M2 M4 transistors were adjusted to obtain a suitable current on M1.

      Different currents were obtained by changing the width of the PMOS M0. Fig.4 depicts the single-side 16-bit DAC. The DAC required eight different current sources, namely Iunit, 4Iunit, 16Iunit, 64Iunit 256Iunit, 1024Iunit, 4096Iunit, and 16384Iunit . The conventional N-bit thermometer-coded type DAC required at least 2N1 current sources.

      The conventional N-bit binary weighted DAC required N current sources. It is the reason of smaller area for the proposed DAC.

      The aspect ratio of M0M1 were adjusted to obtain the unit current Iunit. 4Iunit, 16Iunit, 64Iunit 256Iunit, 1024Iunit, 4096Iunit, and 16384Iunit were also determined by adjusting the aspect ratio of M5/M6, M10/M11, M15/M16, M20/M21, M25/M26, M30/M31 and M35/M36 .

      Last, a differential 16-bit current mirror DAC were

      constructed using two 16-bit single-ended current mirror DACs.

      Differential mode DAC can increase the linear performance of the proposed construction. Compared to the binary weighted DAC, the construction partially used thermometric code, and slightly decreased the glitch.

   3. SIMULATION RESULTS

The differential mode DAC was implemented using CMOS process. The voltage of the circuit was 3.5 V. Which was feed by Agilent pattern generator. Therefore, the sampling rate was set at 350 MHz the output was measured using Agilent oscilloscope. The average INL and DNL were about +0.27/0.17 LSB and +0.32/0.1 LSB, as shown in Figs.5 and 6, respectively.

Fig. 5 INL of 16-bit DAC

Fig. 4 A 16 bit single-ended current mirror DAC

Fig. 6 DNL of 16-bit DAC

Fig. 7 SFDR (Spurious-Free Dynamic Range)

Spurious-Free Dynamic Range (SFDR) is the strength ratio of the fundamental signal to the strongest spurious signal in the output. It is also defined as a measure used to specify analog-to-digital and digital-to-analog converters (ADCs and DACs, respectively) and radio receivers. SFDR is defined as the ratio of the RMS value of the carrier frequency (maximum signal component) at the input of the ADC or DAC to the RMS value of the next largest noise or harmonic distortion component at its output.

Fig.8 Power

Fig. 9 Current

VI. PERFORMANCE SUMMARY

Table. 1

Table. 1 summarized the specifications averaged of all the DAC chips. The power efficiency is 66.903 nW/ 350MHz It is also the smallest among for CMOS technology.

The core size of the chip is also the smallest one. The reason is that the DAC requires only one current mirror for 2-bit conversion. It is suitable for low power and small-area DAC applications, especially for portable device.

The 16-bit proposed DAC has some interesting characteristics. It requires eight current sources of different weight, i.e., 20Iunit, 22Iunit, 24Iunit, 26Iunit. 28Iunit, 210Iunit, 212Iunit, and 214Iunit. However, conventional 16-bit binary- weighted DAC requires 16 current sources of different weight, i.e., 20Iunit,21Iunit,.. 214Iunit, and 215Iunit. Therefore, the proposed approach meets less mismatch problem of current sources compared with binary weighted DAC. The conventional 16-bit thermometer-coded type DAC required at least 215 current sources. The proposed 16-bit DAC required only 8 current sources. It is the reason of smaller area for the proposed DAC.

The approach uses thermometric code in 2-bit DAC. It slightly decreases the glitch during digital code switching compared with binary weighted DAC.

The proposed DAC was sensitive to the resistances of M2, M3, and M4 in Fig. 3 The sensitivity of the resistance would degrade the performance of linearity. It is possible the only disadvantage.

Fig.10 Voltage

Under the sampling rate of 350 MHz, the 2.7 MHz digitized sine waveform was feed into the chip. The SFDR was about

-37 dB, as shown in Fig.7 The full-scale output was 16.255 mV. The power consumption was 66.903 nW at the sample rate of 350 MS/s.

V. CONCLUSION

Most physical variables are analog in nature. Quantities such as temperature, pressure and weight can have an infinite number or values. Converting an analog value to a digital equivalent (binary number) is called digitizing the value. Such operation is performed by an Analog-to-Digital Converter (ADC). After processing the digital data, it is often necessary to convert the results of such operation back to analog values; this function is performed by a Digital-to- Analog converter (DAC). The Multiuse simulator is a useful tool to perform theoretical and practical experiments to

improve understanding of the various electronic concepts. It is also helpful to design and program embedded system applications in our further research work. It also can debug, execute verify results before real time implementation. Experiments were performed on A 16-bit differential mode current steering DAC is proposed in this paper. The DAC was implemented using GDI Logic in CMOS Technology. Eight different unit current mirrors were used to form the 16- bit DAC. The full-scale output was 16.255 mV. The DAC consumed 66.903 nW for 2.23 MHz analog signal at 350 MS/s. The INL and DNL were +0.26/0.17 LSB and

+0.31/0.09 LSB, respectively. Therefore, the circuit was found to consume less power and core area. It is suitable for low power and small-area DAC applications, especially for portable device.

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