A Review on Low Power Designs of Operational Transconductance Amplifier with Linearity Techniques

A Review on Low Power Designs of Operational Transconductance Amplifier with Linearity Techniques

Vidhata Poddar

(M.Tech student) Electronics and telecommunication

DIMAT, Satya vihar Raipur (C.G.), India

Prof. Zoonubiya Ali

(Head of Dept.) Electronics and telecommunication

DIMAT, Satya vihar Raipur (C.G), India.

Abstract: In this paper the relationship among power consumption and linearity performance of CMOS OTA for RF applications are studied, that are illustrated in different literatures. Comparison among the OTA are done in terms their linearity, technology, supply voltage, power consumption, current consumption, open loop dc gain and unity gain frequency. This paper helps the future researchers to design better OTA in terms of linearity, low power consumption and high frequency of operation.

KeywordsCMOS, IC (Integrated circuit), low power, linearity, low voltage, OTA (operational transconductance amplifier), deep submicron, RF (radio frequency).

1. INTRODUCTION (Heading 1)

   In portable high performance, high density ICs the power consumption should be considerably minimized. This, in turn shrinks down IC both in terms of area and power supply. Hence ICs are required to be designed in deep submicron technology with low voltage and power supply. OTA are widely use in wireless analog processing applications such as continuous time OTA-C filters, four quadrant multiplier, mixer, modulator ,data converter, variable gain amplifier, oscillators and other interface circuits. In many of these applications OTA at the input stage determines the overall linearity of the system [1]. So, it is required to improve the linearity of OTAs. As device sizes, supply voltage and power consumption are scaled down to achieve higher operating- speeds, obtaining high linearity with reasonable output signal levels becomes ever challenging. Several circuit techniques have been proposed in literature to improve the linearity of MOS transconductors. These linearity techniques are discussed in section II.

2. TRANSCONDUCTANCE POWER MINIMIZATION LINEARITY ENHANCEMENT

   TECHNIQUES

   In this section various linearity techniques are assembled at once from previously reported literatures to facilitate development of enhanced transconductors. Linearity is important constraint to make the input stage of the OTA output more reliable also the better is the linearity of transconductor the better is the reconstruction of input signal at the output. OTA generates output current for input voltage

   signal and act as a VCCS (voltage controlled current source) [3]. Linearity of the transconductor can be defined on the basis of linear relationship between output current and the differential input voltage. Linearity also means that the transconductance is constant for wide range of input voltage swing [3]. The techniques reported in pervious literature for low power input transconductor are: – a) Floating gate MOS differential pair [10, 12]. b) Bulk driven MOS differential pair [5, 14]. c) Pseudo differential MOS transconductor [8, 11]. To enhance linearity we can adopt: – a) Source degeneration [6, 17]. b) Bias offset technique [7]. c) Adaptive biasing [9]. d) Cross coupling [10, 18]. e) Class AB linearization technique [4, 13]. Among these mentioned technique adaptive biasing can be used for both linearity and as a low power technique.

   1. DETAILS OF THE LINEARITY AND LOW POWER TECHNIQUE MENTIONED ABOVE: –

      1. FLOATING GATE LOW POWER TECHNIQUE

         In [10], a low voltage class-AB OTA fig 1 using the quasi floating gate MOSFET (QFG-MOS) is proposed. It is known that QFG-MOS is suitable for low voltage operation [9]. The circuit uses positive feedback to enhance the input impedance, and novel feed-forward technique to simultaneously suppress common-mode signals and enhance the differential-mode signals. The circuit exhibits large input/output swing with good linearity.

         Figure 1: Single ended class AB linear OTA

         The differential OTA in Fig. 2 is known as Pseudo- differential amplifier (PDA). One can see that the differential- mode transconductance (Gdm) is the same as the common- mode transconductance (Gcm), making the OTA prone to interferences and supply noises. To suppress the common- mode response, a newly developed feed-forward circuitry has been proposed. The technique employs feed-forward amplifier (FFA) and body-driven as shown in Fig. 2. As seen, FFA consists of two independent CMOS inverters (M2AN,P and M2BN,P) and inverting amplifiers (A), which serves two purposes: 1) to suppress the common-mode current signals (io1 and io2), and 2) to enhance the differential transconductance (Gdm) of the system.

         From Fig. 2, the differential-mode (Gdm) and common- mode (Gcm) transconductance gains can be derived and shown as

         Gdm= gm2N, P + A gmb2N, P

         Gcm=gm2N,P-Agmb2N,P (1)

         Figure 2: Proposed class-AB linear OTA

         Where A is the voltage gain of the inverting amplifier, gm2N, P and gmb2N, P are the gate and the body transconductance of M2AN, P (M2BN, P), respectively. The proposed QFG-inverter is employed, enabling the circuit to operate under low voltage supply. Feed-forward technique is used to suppress the common-mode response. The circuit demonstrates wide input/output swing and good linearity over an entire range of the input signal. The differential-mode gain is increased, while the common-mode gain is suppressed.

      2. BULK DRIVEN LOW POWER TECHNIQUE

         One major limitation of conventional OTAs is its limited linear range. As device sizes are scaling down, traditional saturation-based OTAs are facing design challenges to overcome poor linearity and limited output impedance. Bulk driven technique is come into practice for low threshold voltage devices for proper scaling of supply voltage that must be done to appropriately bias the device. In this method the gate-to-source voltage is set to a value sufficient to form inversion layer while the input signal is applied to bulk terminal. In gate-driven MOS transistor the gate-to-source voltage controls the drain current of the transistor while for a bulk driven MOS transistor where, threshold voltage is a function of the bulk-to-source voltage, controls the drain current. Using this technique, transistor can remain in active

         mode even at zero-input bias voltage and also significant improvement in input common-mode range (ICMR) can be observed. However, there are few drawbacks in bulk-driven transistors like one most important drawback is its low dc gain [5]. The current expression for well-input MOS transistor in sub-threshold mode is given by:

         = /(1 )/ (2)

         Where Vgs and Vws is the gate-to-source and well-to source voltage, k is sub-threshold exponential coefficient (generally greater than 0.5), Io is sub threshold exponential parameter, VT (kT /q) is thermal voltage. From (1), it can be observed that dependence of k on gate and (1 k) on well creates the condition that when gate is active, well remains inactive and when well is active gate is inactive.

         The architecture of OTA using modified Wilson current mirror is shown in Fig. 3. The architecture works on low supply thereby introducing appreciable reduction in power consumption and increases the open loop dc gain. With the replacement of simple current mirror by modified Wilson circuit there is sufficient increase in out r and slight decrease in overall transconductance gM. A bias current generator circuit is attached to OTA which generates current in the range of nano-amperes.

         This paper [5] explored the approach of low-voltage OTA desin using the bulk-driven technique and enhancement of gain through Wilson mirror. The design of such low voltage, high performance OTA circuit on TSMC 0.18 micron technology satisfies the required parameters for its implementation not only in power-saving devices but also in biomedical portable devices like biomedical implantable sensors, disk read channel integrated circuits (ICs), video filters, ADSL front-ends, and RF ICs. However, since several biomedical signals have frequencies much less than 609.46 KHz, so less emphasis has been made on achieving high UGB rather enhancement in DC gain has been done.

      3. PSEUDO DIFFERENTIAL AMPLIFIER LOW POWER TECHNIQUE

         Many approaches have been proposed to design low voltage OTA using pseudo-differential (PD) configurations. PD is based on two independent inverters without tail current source. It is known that avoiding the voltage drop across the tail current source, in a PD structure, allows wider input and output ranges, and makes the architecture attractive for low power supply applications. However, PD structure requires an extra common-mode feedback (CMFB) circuit, which serves two purposes: 1) to fix the common-mode voltage at high impedance nodes and 2) to suppress the common-mode signal components. As shown in fig.4 the pseudo differential amplifier has an internal input common mode detector (M1, M2) and a feed forward path M4 to remove DC component of the output current. The node named Vcm contains common mode information of the input signal. Since this Gm cell is usually used in a chain structure i.e. in Gm-C filter its

         common mode extracting feature can help the previous blocks to have a better estimation of their output common voltage.

         MOS Transconductors with Resistive Source Degeneration

         In the following analysis we will consider perfectly quadratic I-V characteristics for the MOS transistors in the saturation region and the channel length modulation effect will be neglected for simplicity. Therefore, the drain current is given by

         = ( )2

         2

         (5)

         Where is the transconductance parameter and is the VT threshold voltage of the MOS transistor. Using (5) the simple differential MOS transconductor shown in Fig. 4(a) has a transfer characteristic given by

         Figure 3- OTA using bulk driven and modified Wilson mirror

         =

         2 1 2

         8

         Considering the non-linearity of the transistor and expressing in terms of Taylor series as:

         I=Idc+a1v1+a v 2+ (3)

         Better linearity can be achieved for large effective gate-to source voltages, VGS, off=VGS VT. For low-voltage applications this constitutes a major drawback. One of the

         simplest topologies to linearize the transfer characteristic of the MOS transconductor is the one with source degeneration

         2 2

         using resistors and depicted in Fig. 6(b). The disadvantage of

         The total expression for Vcm can be expressed as:

         Vcm=gm3 (I1+I2) =gm3[2a2(Vac)2+ 2a4 (Vac) 4 +..]

         (4)

         Figure 4: Basic pseudo differential amplifier structure

         Equ.4 shows that with the same input gm and the power of output current is twice in fig.5 as compared to fig.4.

      4. SOURCE DEGENERATION LINEARITY TECCHNIQUE

         Next technique is for linearization is based on source degeneration technique which is further used two techniques based on the use of resistors and the MOS transistors. Each one has their own advantage and disadvantage.

         this configuration is the large resistor value needed to achieve a wide linear input range. Since in this case Gm=1/R, the obtained transconductance is restricted to small values. Moreover, this technique eliminates the electronic tuning capability of the transconductance because its value is set by the degeneration resistor.

         MOS Transconductors With Source Degeneration Using MOS Transistors

         By replacing the degeneration resistors with two MOS transistors operating in the triode region, the circuit in Fig. 7 is obtained. Considering perfectly matched transistors M1 M2, M3M4, and Neglecting

         Figure (6) 🙁 a) Simple differential MOS transconductor.

         (b) MOS transconductor with resistive source degeneration.

         The body and channel length modulation effects, the transfer characteristic of this transconductor is given by

         = 2 1 2 (6)

      5. BIAS OFFSET LINERAITY TECHNIQUE

         Another linearity technique opted [WANG, 7] is the bias offset linearization technique. In this technique linearization is

         Where

         = 1 + 1

         43

         2

         by cross-coupling the outputs of two offset biased and matched differential pairs as shown in Figure 8.

         Usually, the nonlinear term under the square root can be made much smaller than unity and improved linearity and larger input dynamic range can be obtained. However, increased linearity means smaller equivalent transconductance and reduced tuning capability. The circuit has bandwidth and noise performances comparable to the simple differential pair.

         When the input voltage increases beyond a certain value

         Figure 8:- MOS transconductor using bias offset technique

         vi >4

         1 12+22

         One of the two degeneration transistors enters in the saturation region (M4 for Vi>0, respectively M3 for Vi<0). The output differential current in this case is given by

         Io= (vi1(4a2)+(4a2)Io1vi2) 2

         4a1

         When the amplitude of the input signal rises, the triode- mode degeneration MOS resistors will be more biased such that the synthesized resistance is reduced. This allows less degeneration and results in more gm of the differential pair to compensate for the drop of gm. The quantitative relationship is expressed as follows:

         Gm= [4Kn1 Kn2 (VGS1Vthn) ] /[(4Kn3 – Kn1)n1]

         Assuming the drain current of an MOS transistor obeys the square law characteristics, ID of M1-M4 are expressed as

         ID1=KN (Vin+VSVTHN) 2 (6.a) ID3=KN (Vin-VSVTHN) 2 (6.b)

         ID2= KN (Vin+VB VSVTHN) 2 (6.c) ID4=KN (Vin-VBVSVTHN)2 (6.d)

         Where Vs is negative supply and KN is an ideal transconductance factor, VTHN is the threshold voltage of M1- M4, respectively. The output current Iout is expressed as

         Iout= (ID1ID3)(ID2 ID4) (7)

         Assuming that the input voltage is a fully differential signal, the input voltage Vin is expressed as

         V in = V in+ – V in-= 0 (8)

         From equation (2) – (4), the relation between the input voltage Vin and the output current Iout is expressed as

         Iout=2KNVB V in

         Gm=

         =2KNVB

         (9)

         FIGURE 7: – Transconductors Using MOS Transistors Source Degeneration

         From equation (5) Gm is determined by the transconductance factor KN of M1-M4 and the bias voltage VB. Thus the transconductance is the linear function of output current which governs the linear relationship between input voltage and output current. This is only a first order linearization as it ignores mobility degradation and other higher order effects.

      6. ADAPTIVE BAISING LINEARITY TECHNIQUE

         Above mentioned technique provide only first order nonlinearity cancellation, but it cannot protect the output signal from second order non linearity effects occurred due short channel length due to nano scaling of the device. Adaptive biasing technique is used for improving of the device linearity from second order by employing the MOS transistor as the square law device. Considering quadratic i – v characteristics for the MOS transistors and neglecting the channel length modulation effect, the simple differential MOS transconductor (shown in Figure.6) has a transfer characteristic given by

         If a copy of the current of MC is mirrored into the tail current of basic differential pair the transfer characteristic becomes completely linear according to relation (9):

         +=1 k vi8 2 (10)

         2

         Where k represents the transconductance parameter ( =

         /).

         Better linearity can be achieved for arge effective gate-to source voltages VGSeff =VGS-VTH. For low-voltage applications this constitutes a major drawback. Furthermore, large transconductance values can be obtained only by using large bias currents and large area transistors; however this changes cause to enlarge the power consumption and active area. One of the topologies for linearization of the transfer characteristic of MOS transconductors is using the adaptive Biasing current source. The idea is using a dynamic bias current containing an input dependent quadratic component to cancel the nonlinear term in equation (6). Hence, if the bias is defined as equation

         Figure 10: – Adaptive bias current generator

         io=0.5kVi2 + 8 (13)

         MOS transconductor that uses the linearization approach presented above. The circuit consists of 3 main blocks; an adaptive biasing current generator, a high performance current

         mirror and a main differential pair (fig. 9). MC1- MC4 Formed a high performance current mirror. This circuit copy

         (7),

         =2kIo vi

         (12)

         the dynamic current that produced by Adaptive bias current generator circuit which formed by Ma1, Ma2, Mb and Mc into

         And put this equation in equation (6) the transfer characteristic becomes linear and could be realized according to equation (8)

         =+(2//8) (11)

         Fig.7 shows circuit for generating the adaptive bias current.

         Figure 9:-Simple differential MOS transconductor

         the source of the transistors of main differential pair with source degeneration transistor which formed by M1- M2.

         Figure 11:- The novel linear transconductor

      7. CROSS COUPLING LINEARITY TECHNIQUE

         The cross coupling linearization technique is proposed in [18].Cross-coupled differential pair cancellation technique to significantly minimize the third-order harmonic-distortion component. Consider a matched pair (M,, M2) coupled by two

         voltage sources of equal value (Vth + Vx) as shown in Fig. 11. Representing V1V2 by v,

         ID= (1/2) µn Cox (W/L) (VGS + VTH)

         Gives

         I1=k (Vx + v) 2

         I2=k (Vx – v) 2

         The output current i = I1 – I2, obtained by a simple p- channel current mirror, will be

         I = I1 – I2=4kVxv

         Thus this configuration exhibits a perfectly linear transconductance of value gm = 4kVx.

         Consider implementing the sources (Vth + Vx) by two additional n-channel transistors M3 and IV& biased by constant currents. Note that Ml and M4 share a p-well connected to their common source node, whereas M2 and I& are in a separate well to avoid back-gate bias effects. For obtaining reasonable voltage sources with low source impedance, these devices must be wide and biased with currents that are large compared to the signal currents through them. The resulting circuit is a cross-coupled quad configuration shown in Fig. 13. M1, M2, M3, and M4 have the same channel length, but M3 and M4 are made n times wider than M1 and M2. For maintaining the same value of

         Vb=(/), M3 and M4 are biased with nI.

         Figure13:- Linear transconductance the cross-coupled quad configuration

         Class-AB OTAs have been designed using two approaches: increasing the tail current of the differential input pair for large input signals or increasing the current in the active load of the differential input pair.

         The class AB V-I linearization technique can be shown in fig.14. In this topology, the transistors M3, M4,M5, M6 are biased in triode region, therefore the voltage at drain of M1, M2 would be very close to supply voltage and the source voltage can be as low as several tens mV and can here be neglected [13]. The transfer function is given by

         I =Im -Im =nKn(VcmVtn )(Vnl2Vtn)V (14)

         out 7 8 2() id

         Figure 12: – Linear transconductor.

      8. CLASS AB LINEARITY TECHNIQUE

         When the OTA is employed with negative feedback (as an op-amp) in applications such as SC circuits or buffers for driving capacitive loads, it must exhibit a large slew-rate and sufficient gain-bandwidth product (GBW) in order to achieve a fast settling response. As it is known, Class-A circuits cannot achieve these requirements without significantly increasing their power consumption.

         Where Kn, Kn, Kp are transconductance parameter of NMOSs (M1, M2), (M7, M8), and PMOS (M3, W4),

         respectively. Vtp is threshold voltage of PMOS. Vid = Vin+ V-

         b

         in- , V = Vdd -Vb, Vnl V1+V2-2Vs, M7, M9, and V1-V2=Vd, M3-

         Vd,M4. As can be seen from (14) that the output current Iout is a function of the differential input voltage Vid. V1 and V2 are very close to Vdd, thus V1+ V2 is almost constant and its nonlinear effect can be ignored. However, with the supply voltage lower than 2V, nonlinear term can be occurred

         Figure 14:- Class AB Transconductor

3. CONCLUSION

There are three basic requirements of present and future techniques they are: – I) low voltage. II) High linearity. III) High frequency. (I) and (III) can be achieved optimally by downscaling of device size. As the voltage decreases the range of input voltage swing decreases or we can say that the higher voltage swing gets distorted which imposes linearity issue on the input stage of the OTA, technique for linear performance of input stage for OTA presented in paper from previous works can be used. Using of more than one linearity and power optimization technique can optimize the design suitable for any application. Each of the techniques has their own advantages and disadvantages. So the techniques should be used according to design requirement only.

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