Triangular Gate-all-around Nanowire FETs with Enhanced Electrical Performance using High-K Dielectric Gate Oxide

Triangular Gate-all-around Nanowire FETs with Enhanced Electrical Performance using High-K Dielectric Gate Oxide

Ankit Gaurav

Department of Electronic and Communication Engineering Guru Nanak Dev Engineering College

Ludhiana, India 141006

AbstractIn this paper the enhanced electrical performance of Triangular Gate-all-around Nanowire FETs has been reported using High-K dielectric gate oxide for 14 nm gate length. It was found that by using High-K dielectric material like Hafnium (IV) oxide instead of using Silicon Dioxide the electrical performance improved significantly. ON-OFF Current ratio improved by

1. %, Drain Induced Barrier Lowering reduced by 33.33 %, Sub threshold Swing reduced by 1.53%, Off state leakage current reduced by 18.50% and on current increased by 132.26%. 3D Technology Computer-aided Design numerical simulator was used to perform all device simulation using Drift Diffusion approach with Density Gradient Quantum Corrections model.

   Keywords Gate all around, FET, High-K dielectric and Numerical Simulation.

   1. INTRODUCTION

      In this last decade, due to continuous downscaling of silicon MOSFETs the short channel effects (SCE) has become a major concern in order to meet the International Technology Roadmap of Semiconductors (ITRS) projections [1-4]. In this context, Gate-all-around (GAA) Nanowire FETs are consider as a promising transistor structure, which enables further gate length scaling beyond 22 nm because of its superior SCEs immunity realized by all around gate structure [5-6].

      The insulator layer in the field effect transistors system electrically separates the different semiconductor region like source, drain and channel from the gate electrode, while simultaneously serving as a medium transferring the field effect of the gate electrode in the semiconductor region. The thinner the insulator layer, the higher the electron concentration induced at the semiconductor surface. Additionally, thinning the insulator layer shields the channel carriers from the fringing field lines originated in the drain, thereby reducing SCEs. Thus, the SCEs of GAA Nanowire FETs can be further reduced by scaling down the gate oxide layer. However, scaling of silicon based oxide below 2 nm results in an increase of gate tunnel leakage current [3]. Intel in 2007 introduced Hafnium-based oxides as a replacement for silicon oxide as a gate insulator in MOSFETs in 45nm technology [7]. In the previous reported work the use of dielectrics with high permittivity (high-k dielectrics) instead of silicon dioxide has shown the further scaling of gate oxide with performance improved of conventional MOSFETs and FinFETs [8-10].

      Fig. 1 Systematic diagram of Fin cross section view of Triangular GAA Nanowire FETs

      In this paper the comparative electrical performance analysis of Triangular GAA Nanowire FETs with High-K Dielectrics material Hafnium (IV) oxide (HfO2) and Silicon Dioxide (SiO2) has been done in terms ON current, OFF current, Drain Induced Barrier Lowering and Sub Threshold Swing for 14 nm gate length. The systematic diagram of fin cross section has been shown in the Fig. 1. This paper has been presented in the following manner Section 2 describes the device design and simulation approach. Section 3 shows the results and discussions of the proposed work. Subsequent Section concluded the work.

   2. DEVICE DESIGN AND METHODOLOGY

      Triangular GAA Nanowire FETs structures was designed by using Cogenda GDs2mesh 3D Technology Computer-aided Design numerical simulator (TCAD) model construction tool [11]. Triangular Fin of GAA Nanowire FETs was designed with the bottom fin width (Wfin, bot) of 10 nm and top fin width (Wfin, top) of ~ 0 nm. Non-vertical sidewalls was taken symmetric with equal swings of the lateral sides. The nominal device parameters have listed in Table I. The 3D illustrations of the designed Triangular GAA Nanowire FETs devices is shown in Fig. 2. Fig.2 (a) show the active region fin of the device which of triangular shape. Fig.2 (b) show the source pad, drain pad, active region that was etched on substrate. The active region was etched at height of 30 nm above the substrate this 30 nm represent the shallow trench isolation of the device. Tungsten with work function 4.50eV was used for metal gate.

      TABLE I. DEVICE PARAMETERS

      Parameter	Value
      Gate Length	14 nm
      Fin Height	30 nm
      Gate Oxide Thickness	1 nm
      Top Fin Width	~ 0 nm
      Bottom Fin Width	10 nm
      Source/Drain Doping(donor)	11020 cm-3
      Substrate Doping (acceptor)	11017 cm-3

      Fig. 2 (c) shows the metal gate and metallic contact aluminum that was used for power supply. Finally, to separate different region from each other the silicon dioxide was formed as shown in the Fig. 2 (d). Similarly for the second device Hafnium (IV) oxide was formed to separate different region from each other as shown in the Fig. 2 (e) keeping all other parameters and process same as that of Triangular GAA Nanowire FETs with Silicon Dioxide dielectric. Fig. 2 (f) shows the color index for different material. Lightly doped silicon channels are used to reduce random dopant fluctuation and to eliminate the threshold voltage and mobility variability [4]. For substrate the doping concentration is 1e17 cm-3 of acceptor type and is doped uniformly. For source/drain the doping concentration is 1e20 cm-3 of donor type and the doping profile is Gaussian.

      Triangular GAA Nanowire FETs devices has been simulated using Cogenda Visual TCAD numerical simulator. The carrier transport was defined using classical drift diffusion (D-D) approach with density gradient approach based quantum corrections [12]. In order to characterize the electrical performance of GAA FETs accurately, it is important to consider quantum confinement effects. The most acceptable choice for the inclusion of quantum corrections in D-D simulations is the density gradient approach [13].The Carrier transport is defined using D-D model which mainly uses Poissons equation can be expressed as follows:

      . = q(p n + + ) (1)

      For inclusion of Quantum confinement effects can be included in D-D model by including the quantum potential in calculating the driving force of electrons and holes. This correction term is related to the density gradient of carrier concentration [13-15].

      =

      2

      (2)

      =

      2

      (3)

      Where is the electrostatic potential of the vacuum, n and p are the electron and hole concentration respectively, + and

      are concentration of donor and acceptor ions respectively

      Fig. 2 Birds eye view of Triangular GAA Nanowire FETs illustrations; (a) Triangular Fin shape active region, (b) Active region with source and drain pad, (c) Formation of metallic gate and power supply contact, (d) Formation of silicon dioxide to separate each layers, (e) Formation of Hafnium (IV)

      and is electron charge.

      = 2

      6

      and

      = 2

      6

      are the

      oxide to separate each layers and (f) color index for different material.

      coefficients with and being the electron and hole effective masses respectively.

   3. RESULT AND DISCUSSION

      The threshold voltage was calculated using mximum Trans conductance change method for both Triangular GAA Nanowire FETs directly from its V-I characteristics with drain voltage of 50 mV [16].

      The on-current was measured at gate voltage, = 1V and off- current at = 0V in the linear region with drain voltage of 50 mV. The sub threshold swing is the change in the gate voltage per decade change in drain current.

      = ( ) (4)

      The DIBL parameter is the horizontal displacement of the transfer characteristics at constant drain current ( ) for drain voltage = 0.02 and 1V [17].

      = ( ) × 107

      (5)

      The effective channel width, ( ) for Triangular GAA Nanowire FETs is define as

      = 2, + 2 (6)

      The fin width () for Triangular GAA Nanowire FETs varies in the range of top fin width (,) and bottom fin width(,). The equivalent fin width , of Triangular GAA Nanowire FETs can be given at its orthocenter [17].

      Fig. 3 Simulated V-I characteristics (a) Transfer characteristics in linear and logarithmic scales and (b) Output characteristics of Triangular GAA Nanowire FETs with silicon dioxide as dielectric.

      ,

      = ,

      +

      + 1

      (,

      ,

      ) (7)

      2, + ,

      = 2, + ,

      (8)

      The simulated V-I characteristics of Triangular GAA Nanowire FETs with silicon dioxide dielectric and with Hafnium (IV) oxide dielectric have been shown in the Fig. 3 and Fig. 4 respectively. The transfer characteristics has been plotted for drain voltage of 50 mV and 1V in linear as well as logarithmic scale and the output characteristics for different gate voltage ranging from 0.6 to 1.2V. The calculated electrical parameter value of both Triangular GAA Nanowire FETs have been listed in the Table II. By replace the silicon dioxide dielectric with high-k dielectrics Hafnium (IV) oxide of Triangular GAA Nanowire FETs the off state leakage current reduced by 18.50%, on current increased by 132.26%, ION/IOFF ratio improved by 184.99 %, DIBL reduced by 28.20 % and SS reduced by 1.53%. The threshold voltage was almost same for both Triangular GAA Nanowire FETs because of the lightly doped channel. The transfer characteristics comparison of Triangular GAA Nanowire FETs with silicon dioxide and Hafnium (IV) oxide for drain constant voltage of 50mV is shown in the Fig. 5.

      Fig. 4 Simulated V-I characteristics (a) Transfer characteristics in linear and logarithmic scales and (b) Output characteristics of Triangular GAA Nanowire FETs with Hafnium (IV) oxide as dielectric.

      TABLE II. ELECTRICAL PARAMETERS OF SIMULATED TRIANGULAR GAA NANOWIRE FETS.

      Parameter	Triangular GAA Nanowire FETs (SiO2)	Triangular GAA Nanowire FETs (HfO2)
      VT (V)	0.241	0.245
      ION (A)	9.21E-06	2.14E-05
      IOFF (A)	6.02E-11	4.91E-11
      ION/IOFF	1.53E+05	4.36E+05
      DIBL (mV/V)	48	32
      SS (mV/dec)	65	64

      Fig. 5. Comparison of simulated transfer characteristics of Triangular GAA Nanowire FETs with Hafnium (IV) oxide and silicon dioxide as dielectric for Vd = 0.05 V.

      The above simulation results of Triangular GAA Nanowire FETs have shown that high-k dielectrics Hafnium (IV) Oxide can improve the device performance and also it can be used to further scale down the gate oxide below 2nm. This improved in electrical performance is due to high dielectric constant of HfO2 which is 46 times higher than that of SiO2.

   4. CONCLUSION

The electrical performance analysis of Triangular GAA Nanowire FETs with silicon dioxide and Hafnium (IV) oxide for 14 nm gate length have shown that the high-k dielectrics Hafnium (IV) oxide can improve the devices performance of GAA Triangular FETs. This improvement is due to high dielectric constant of Hafnium (IV) oxide. Gate oxide thickness can be further scale down below 2nm using High k dielectric material like Hafnium (IV) oxide. The scaling down of gate oxide thickness improve gate controllability of channel and hence reduction in short channel effects.

REFERENCES

1. R. Dennard, F. Gaensslen, V. Rideout, E. Bassous, and A. LeBlanc, Design of ion-implanted MOSFETs with very small physical dimensions, IEEE J. Solid-State Circuits, vol. SSC-9, no. 5, pp. 256- 268, October 1974.

2. J. Park and J. Colinge, Multiple-gate SOI MOSFETs: Device design guidelines, IEEE Trans. Electron Devices, vol. 49, no. 12,pp. 2222- 2229, December 2002.

3. J. Colinge, FinFETs and Other Multi-Gate Transistors, New York, NY,USA: Springer-Verlag, 2008.

4. W. Xiong, J. Park and J. Colinge, Corner Effect in Multiple-Gate SOI MOSFETs, IEEE Electron Device Letters, vol. 37, no. 14, pp. 111-114, December 2003.

5. N. Singh, A. Agarwal, L. Bera, T. Liow, R. Yang, S. Rustagi, C. Tung,

   R. Kumar, G. Lo, N. Balasubramanian, D. Kwong, "High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices," in Electron Device Letters, IEEE , vol.27, no.5, pp.383-386, May 2006.

6. Y. Hashim, O. Sidek, "Effects of Diameter of P-channel Nanowire Transistors on Nanowire-CMOS Inverter Characteristics," in Computer Modelling and Simulation (UKSim), 2012 UKSim 14th International Conference on , vol., no., pp.678-681, 28-30 March 2012.

7. Online].Available: http://www.intel.com/pressroom/archive/releases/2 007/20071111comp.htm

8. E. Litta, P. Hellstrm, and M. Ostling, Integration of TmSiO/HfO2 Dielectric Stack in Sub-nm EOT High-k/Metal Gate CMOS Technology, IEEE Transactions On Electron Devices, Vol. 62, No. 3, pp. 934-939, March 2015.

9. K. Boucart and A. Ionescu, Double-Gate Tunnel FET With High- Gate Dielectric, IEEE Transactions on Electron Devices, vol. 54, no. 7, pp. 1725-1733, July 2007.

10. A. Gaurav, S. Gill, and N. Kaur, Performance Analysis of Rectangular and Trapezoidal TG Bulk FinFETs for 20 nm Gate Length, 12th IEEE Indicon International Conference, Jamia Millia Islamia, New Delhi, India, December 2015.

11. [Online]. Available: http://www.cogenda.com/article/Gds2Mesh.

12. [Online].Visual TCAD Brochure Available: http://www.cogenda.com/article/downloads.

13. Loureiro, N. Seoane, M. Aldegunde, R. n, A. Asenov, A. Martinez and

    K. Kalna, Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors, IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, Vol. 30, No. 6, pp. 841-851, June 2011.

14. M. Fourni, High order conservative difference methods for 2-D drift diffusion model on non-uniform grid, Appl. Num. Math., vol. 33, nos.14, pp. 381392, May 2000.

15. F. Pregaldiny, C. Lallement, and D. Mathiot, Accounting for quantum mechanical effects from accumulation to inversion, in a fully analytical surface-potential-based MOSFET model, IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 781787, May 2004.

16. H. Wong, P. White, T. Krutsick, and R. Booth, Modeling of transconductance degradation and extraction of threshold voltage in thin oxide MOSFETs, Solid-State Electron., vol. 30, no. 9, pp. 953968, 1987.

17. N. Fasarakis, T. Karatsori, A. Tsormpatzoglou, D. Tassis, K. Papathanasiou, M. Bucher, G. Ghibaudo, and C. Dimitriadis, Compact Modeling of Nanoscale Trapezoidal FinFETs, IEEE Transactions on Electron Devices, vol. 61, no. 2, pp.324-332,February 2014.