A Novel on Design and Analysis of on Chip Low Drop out Regulator for Improving Transient Response

A Novel on Design and Analysis of on Chip Low Drop out Regulator for Improving Transient Response

Harish R

PG Student,

Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology,

Surat, India

Abstract: In Power management of System on Chips On chip (SOC) Linear Low Drop out (LDO) Regulators are dominating compared to other regulators. In LDOs Analog circuits playing an important role in the control of switching power supplies because of its simplicity and less expensive. To meet the increasing requirements of present and future processors with low voltage and higher load currents, a LDO with better transient performance is must. This lead to design a LDO with compensator which will make the loop stable for all load current variation. In this paper, a prototype of pole-zero(PZ) compensator for linear voltage regulator is designed for system level integration. Based on the frequency behavior analysis of the linear regulators, a PZ compensation scheme is presented for the PMOS linear regulator. This PZ scheme is able to control the large frequency variation of the PMOS linear regulator output pole. The effectiveness of PZ compensation is examined by mathematical modeling in Matlab and Simulink. Using this system level (high level) analysis of plant transfer function yields to design a controller for faster response of LDO.

Keywords : LDO, PZ, Transient response, SOC.

1. INTRODUCTION

   Scaling of transistors have boosted the growth of highly packed designs. System on a chip (SOC), integrates all components of an electronic system on a single chip. The high computing power of a large number of transistors, powers multi-core SOCs. But increased frequency of operation due to device scaling also results in larger power dissipation, with power numbers rising proportionately with faster computations. Multi core systems that run multiple processes, need power management techniques for efficient operation. These units control the regulated voltage for the system. The power supply module needs to be integrated into the design itself with voltage references, regulators and controllers. A faster computation consumes more power and also increases the frequency of load transitions. Hence a voltage regulator with higher efficiency and faster transient response, with minimum power dissipation is needed to be used in multi-core SOCs. The regulated voltage for a SOC is generated from an external supply voltage with a Band Gap reference as shown in Figure 1.

   Mehul C Patel

   Assistant Professor, Department of Electronics Engineering,

   Sardar Vallabhbhai National Institute of Technology, Surat, India

   Fig 1. Simple LDO topology

   Low Drop out Regulators

   The output voltage of a regulator should have minimal changes in its output level with respect to variations in the process, input voltage, noise, temperature and other factors. Supply level gets reduced by an amount of VDROP due to the saturation drop across the regulator. This loss needs to be small especially in current system designs with supply voltages being close to 1V. The quiescent current IQ drawn by the regulator for its internal operation, accounts for the difference between input and output currents of the regulator. Dropout voltage refers to the input-to-output differential voltage at which the module fails to regulate the input supply. This point occurs when input level approaches the output voltage.

   The rest of this paper is structured as follows: Section II presents the system model of LDO, in Section III, shows procedure to design compensator. Section IV shows the simulation results with droop and overshoot analysis. Finally, Section V concludes the paper.

2. CONVENTIONAL LINEAR LDO

   This section of the paper presents about analog LDO and some of the theoretical aspects used through the paper.

   In general, large voltage drops reduces the efficiency of regulators [1]. If we ignore the dissipation loss due to the non- ideal elements, its efficiency can be derived through the following set of equations:

   = (1)

   = ( + ) (2)

   = = =

   =

   +

   +

   +

   (3)

   Equation (3) highlights the need to reduce the drop across the regulator and the bias current IQ. Hence the design of LDO is important to increase its efficiency. A voltage regulator is similar to a voltage controlled voltage source (VCCS) with requirements of low output resistance ROUT. This can be achieved by employing a negative feedback system as discussed in subsequent section.

   Conventional PMOS LDO

   Voltage regulators operate in saturation region where the transistor acts as a voltage controlled current source. Under varying load conditions, Vgs controls the low drop out regulator to supply the load current. This allows the voltage drop from the unregulated voltage to regulated voltage to be as low as saturation voltage across the transistor. The sampling resistors convert the current to voltage according to the following equation (4).

   switching loads conditions. Major factors to characterize LDO performance are settling time, Overshoot, and Voltage droop.

   B. AC Analysis

   Negative feedback systems are inevitable for its advantages of better control. But it brings along stability issues. AC analysis provides information about the circuit bandwidth, cutoff frequency, the gain, the role-off, or any peaking in the frequency response.

   DC gain of the system refers to the flat gain at low frequency before the first 20 dB/decade roll off. 3-dB bandwidth also main factor AC analysis. The main components of AC part to decide system response are Phase margin (PM) and Gain margin (GM). The final key factor is Power Supply Rejection Ratio (PSRR), it gives a performance metric for ripple in the input supply and its effect on the

   = (1 + 1)

   (4)

   output across different ripple frequencies.

   2

   The conventional PMOS LDO is shown in figure 3 with

   The negative feedback loop controls the regulator action and provides the necessary reduction in Rout as given by equation (5).

   load connected. The load capacitor Co with ESR Rc provides pole and zero these two components are main key elements in LDO stability.

   = (

   1 + 0

   ) (5)

   0 1 2

   0 1 2

   where loop gain = 2 , Error amplifier gain

   1+2

   A1=gm*ro, Pass Transistor gain A2=gm0*rmo.

   Low dropout regulators comprise of a voltage reference, a pass transistor element, an error amplifier and sampling resistors as shown below in Figure 2.

   Fig 3. Conventional LDO with Load connected

   () = (1+/)

   (1+ )(1+ )

   =

   (6)

   +

   The overall, Open loop transfer function of the plant is given by

   =

   (1 + /)

   (1 + )(1 + )(1 + ) (7)

   Fig 2. Conventional LDO regulator with analog Controller

   LDO Performance Metrics:

   The validation flow for the design for LDO includes

   where Kdc is low frequency gain of the system. It includes PMOS gain Gdc, feedback gain, and error amplifier gain.

   different parameters. These are enlisted according to the analysis as follows:

   = 1

   [ + ( ||)]

   1. DC Analysis

      DC analysis includes supply voltage has to provide average input supply and also average LDO output. Load

      = 1

      1

      (8)

      current (IL), efficiency of the regulator decreases with increase in Vdrop and IQ. The IL depends on activity of the load. Important DC analysis is Transient Analysis; it refers to

      =

      = 1

      ( ||)/[ + ( ||)]

      where WL is the pole due to load resistance and load capacitor, WZ is the zero produced by ESR, Wopamp is the pole due to operational amplifier and PMOS interaction, Wb is the pole produced by combination of load and bypass capacitor. In coming section detailed analysis is provided about these poles and zeros.

3. COMPENSATOR DESIGN AND ANALYSIS

   The calculated open loop transfer function is having three poles and one zero. Wopamp is insignificant to consider in stability analysis, because frequency of the pole is very high so it becomes insignificant pole. So Gain of opamp will be considered in the analysis. Load pole is the dominant pole which will impact stability. Below figure is the simplified load equivalent circuit.

   Fig 4. Small signal equivalent circuit of Conventional LDO

   Equivalent impedance seen at output terminal is calculated as equation 7.

   The Open loop transfer function (Eq 7) of the feedback loop has three poles, one (Pint) pole due to bypass capacitor, second pole (Pload) pole due to load, Popamp pole due to opamp-PMOS interaction and one Zero (Wz) due to ESR of load capacitor. Pint is fixed at certain frequency, Zesr depends on ESR value, so it is also static zero for certain conditions. Pload is variant to load current due to rds of PMOS and RL are in their expressions. Since Zesr is a high frequency LHP zero because ESR value is very low in the order of milli ohms, so it increases both gain and phase of system at a certain frequency range and possibly makes the feedback loop more stable. Choosing an output capacitor for LDO regulators with PMOS pass element can be difficult due to specific ESR requirements. The optimum ESR capacitors are necessary to get stable response of the system. If you choose ESR value according to your load capacitor range, then Zesr will not impact the stability of the system.

   The only problem creator to the stability of the loop is the output load pole Pload, why because it can change a lot with output load current range. Therefore, the compensation scheme must accommodate the Pload movement with load. In other words, the compensation should provide stability over the load variation or Line variation. The wide variation of load pole Pload creates difficulties for compensation. To overcome problem with this movement or variation of load pole, there are two possible solutions those might be effective are,

   1. Making Pload always out of the expected bandwidth.

   2. Accommodate Pload movement by adding a zero.

   Solution 1 can be implemented by increasing the load current (in mA range) to move Pload to higher frequency why because from equation Pload is inversely proportional to i.e., increase in load current IL cause to decrease RL so that Pload frequency will increases. But this is not acceptable for the low quiescent current requirement in this design [6]. It can also be realized by some pole-splitting methods, which push the output pole out of the bandwidth. However, two reasons make this solution not suitable for this design. One is the gain of MOS power transistor in source follower configuration is near 1 which makes pole spitting very difficult. The other is the large load capacitor (nF) resulting the output pole at relatively low frequency. To push this pole to the higher frequency may require a very large spitting capacitor and high current consumption.

   Fig 5. PZ compensator Solution II

   Solution 2 can be conceptually shown in Figure 5, where Zc is the zero added in the loop. It can be seen that as the load current increases, the output pole Pload moves to the higher frequency. However, due to the existence of Zc, the loop is stable because the phase shift of Pint is compensated by Zc. It is interesting to notice that as Pload goes to higher frequency, the bandwidth also gets extended. This may add advantages on transient performance as the bandwidth of the linear regulator is playing a role in line/load response. It seems that Solution II is a good candidate for the frequency compensation. To compensate this loop, the zero Zc should meet two requirements: One is it must near the minimum frequency of Pload to ensure the low current load stability; the other requirement is the associated pole generated by adding zero Zc should be outside the maximum close-loop bandwidth. The drawback of Solution 2 is the generation of low frequency Zc needs large passive components (big resistor and big capacitor), which requires large silicon area. Also, adding Zc through passive components will bring an associate pole with it [5][6] .

   PZ compensator:

   From above analysis it is clear that the Open loop plant is not stable for varying load currents, because of load pole movement. Henceforth to accommodate problem with load pole Pload, we need to introduce a ZERO before the Pload so that Pload will move out of the bandwidth. Another important performance metric for LDO is settling time, to get faster response bandwidth of LDO as high as possible. To get better bandwidth Gain curve of the system should roll off with slope of -20 dB. So system requires a POLE. By using this analysis, to get improved transient response PZ (pole-zero)

   compensation is necessary. One more important factor for second order system Integrator will provide better transient analysis with low steady state error. Finally, PZ compensator equation as follows:

   (1 + )

   = () () (12)

   Now again find PM and GM check with specifications, if the specs are reached then stop the PID tuning then find the step response of the closed loop system. Else recompute the

   =

   (1 + )

   (10)

   PZ locations by changing gain of the system.

   The above equation represents PZ compensator of PMOS LDO. Kc represents the additional dc gain which will compensate for PMOS and Error Amplifier dc gain. Wzc and Wpc are the zero and poles of compensator. To find the appropriate locations of the Pole and Zero, it is required to follow below procedure:

   Fig 7. PZ compensator BW improvement

4. SIMULATION RESULTS AND DISCUSSION

   This chapter presents the simulated results that characterize the LDO. The results are presented to cover several circumstances that the circuit could be subjected to. The simulation variations are presented with respect to PM and GM.

   AC analysis:

   In this section the AC analysis is performed for the generic process corner, due to the complexity of the circuit. The circuit is simulated and then get the Rds information across different loads and VIDs. Based on Ron information computed plant open loop transfer function. Then designed controller or compensator to get required system specifications.

   Fig 6. PZ-compensator Design flow

   The above flow chart outlines the procedure to design the PZ compensator to satisfy steady-state error and phase margin requirements. First calculate the open loop transfer function (OLTF) then calculate Kc to satisfy the steady-state error. Then find out bode plot of the OLTF G(s) given in equation. Then determine the amount of phase shift in G(s) at the gain crossover frequency and calculate the uncompensated phase margin PM. Find the Phase angle of the system by using,

   = () + 10° () (11)

   Now tan angle of the above phase will give the location of the pole and zero. By using PID tuner in MATLAB, can calculate quickly. After finding PZ locations i.e., calculated compensator, multiply it with OLTF G(s), will get Plant OLTF (POLTF):

   Table 1. Specifications for Analysis

   Vin	1.15
   Vout	1.0
   Vdrop	150 mV
   RI	Vout/Iload
   Rc(ohms)	2
   gm	123 mA/V
   rds	65
   R1(ohms)	64 K
   R2(ohms)	36 K
   Co(F)	15e-9
   Cb(F)	0.5e-9
   Iload	1-10 A

   The above Table describes typical specifications.

   Fig. 8 Open loop Plant Uncompensated Bode plot

   Figure 8 shows that Open loop plant bode plot, there we can observe that GM=infinite and PM = 180o that means this plant cannot improve the transient response at load current, so it is required to design a controller or compensator which brings open loop controller PM to required i.e., 45o. Figure 9 is Compensator bode plot, with PM = 134o at 4.92e9 rad/sec which boosts the Plant to required PM and Bandwidth.

   Fig. 9. PZ Compensator Bode Plot.

   Fig. 10. Plot for compensated Bode plot

   Figure 10 shows that plant is multiplied with compensator and gives the PM of 45o at 2.798e08 rad/sec and GM = 4.9 dB. Figure 12 is, which show step response of the system with time and frequency domain specifications, for this see Table 1.

   Fig 11: Phase and Gain Margin analysis with load current

   Figure 11 shows the phase margin and bandwidth over all current load for regulation loop, it can be observed that the bandwidth of this loop is always higher than 1MHz. The minimum bandwidth is get at the current is at 250mA, which is around 3.5MHz. The bottleneck of the main voltage regulation loop bandwidth should be lower than this value.

   Fig. 12 Bode plot for different load currents

   The above plot represents open-loop bode plot of LDO regulator with PID compensator over different load current is shown in Figure 12. As the load current increasing, the output pole is moving to higher frequency. Owing to the added zero and pole controller scheme, the system stability can be ensured.

   Fig 12: Step response of compensated and uncompensated closed loop system for IL=3A and Vo=1V

   The Step response of overall closed loop is shown in Figure 12. The PM and Bandwidth of the closed loop step response is replicated in this plot. As IL varies from minimum to maximum PM and Bandwidths are also increased, so that transient behaviour of the loop also improves.

   Table 2. Time domain analysis

   Open loop Plant Analysis	Rise Time (ns)	Peak Time (ns)	Settling Time (ns)	PM	GM	BW (MHz)
   Without Compensatio n	80	100	200	35	1.2e4	200
   With Compensatio n	50	75	95	45- 60	4.9 dB	279

5. CONCLUSION

A PZ-Compensator is designed and analyzed in MATLAB. It is observed that this method is a simplest method to improve transient performance of LDO. It also showed that with this method response time decreased from 80ns to 50ns. In future, proposed method will be implemented with transistor level design and will verify droop and overshoot.

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