Low Leakage Cell for Ternary Content Addressable Memory: A Tutorial and Review

Low Leakage Cell for Ternary Content Addressable Memory: A Tutorial and Review

Ankaj Gupta1

1Department of Electronics& Communication Engineering, Ganga Institute of Technology and Management,

Kablana, Jhajjar, Haryana, India

Abstract- Ternary Content addressable Memory (TCAM) has been an emerging technology for packet forwarding in Network Router. New architecture innovations are reducing power and leakage in TCAM. Beside power, leakages also constitute a major part in TCAM performance. In this paper we review various schemes for low leakage TCAM. The circuits have been implemented in 0.35-m CMOS technology. The minimum power supply is 1.5 V and the maximum supply current is 11.5 A for a temperature range of 25°C to 30°C.

Index Terms- TCAM Cell, Leakage Current, Power Dissipation

I. INTRODUCTION

A Content Addressable Memory (CAM) is an outgrowth of random access memory (RAM) technology. Unlike RAMs

identical (the match or are different (a mismatch case, or miss).

II . TCAM CELL

1. Leakage Current Component

   The leakage current of a deep sub micrometer CMOS transistor consists of three major components: junction tunneling current, subthreshold current and tunneling gate current [11]. In this section, each of these three components is briefly described

   1. Subthreshold Leakage Current: Subthreshold leakage is the drain-source current of a transistor when the gate- source voltage is lower than the threshold voltage. The subthreshold leakage is modeled as [11].

      which access a word based on its address, CAMs access a word based on its contents. A CAM compares an incoming

      Isub Asub exp(

      q

      n ' kT

      (VGS Vto 'VSB

      key with all the words in parallel and returns the address of the best match in the array [1]. Therefore CAM is an application specific memory that allows its entire contents to be searched within a single clock cycle. TCAM applications

      VDS )) (1 exp(

      Where

      q VDS ))

      kT

      (1)

      include parametric curve extraction [2], Hough transformation [3], Huffman coding/decoding [4], [5], LempelZiv compression [6]-[9], and image coding [10].Techniques are described to reduce leakage. Fig.1 gives general view of TCAM architecture. The input to the system is the search word that is broadcast onto the search lines to the table of stored data. Each stored word has a matchline that indicates whether the search word and stored word are

      Fig. 1. Schematic of TCAM

      COX = Gate oxide capacitance per unit area W = Width of the Transistor

      L = Effective Length of the transistor K = Boltzmans Constant

      T = Absolute Temperature

      ' = Linearized body effect cofficient

      = Drain induced barrier Lowering (DIBL)

      ' = Subthreshold Swing coefficient of the transistor

   2. Tunneling Gate Leakage Current: Electron tunneling from the conduction band, which is only significant in the accumulation region, results in direct tunneling gate leakage current in nMOS transistors. In pMOS transistors, hole tunneling from the valence band results in the tunneling gate leakage current. If is used for the gate oxide, pMOS transistors will have about one order of magnitude smaller gate leakage than nMOS transistors Therefore, one may conclude that the major source of tunneling gate leakage in CMOS circuits is the gate-to channel tunneling current of the ON nMOS transistors which can be modeled

as [12]

Jtunnel 4 m * q (kT )2(1 kT )

states. Hence, one-third of the bits will be masked and

p

exp( EF

KT

(2)

EB )

2 . EB

setting the BLs to the mask state minimizes the subthreshold leakage. For example, if the BLs are set to 0 (BL1 = 0, BL2 = 1), the subthreshold leakage through

the access transistors will be 2ISN when the stored value is

Where m*(= 0.19Mo) = Electron transfer mass Mo = Electron Rest Mass

h= planks Constant

EF = Fermi Level at the Si/SiO2 interface EB = Height of Barrier

mask. Typically, the driver transistors (NMOS in the cross-coupled inverters) are sized nearly 2 to 2.5 times larger than the access transistors to perform fast READ operation without disturbing the stored data.

4TOX 2mox

h

(3)

I6T_Mask/BLs = Mask = 2ISN + 2ISP + 2IGON + 6IGOFF + 2IGONP

+ 2IGOFFPK (4)

Where mox (= 0.32Mo) = Effective Electron Mass in the Oxide

The major contributor to the tunneling gate leakage current in a 6T SRAM cell is the gate-to-channel leakage of the ON pull-down transistor. To weaken this leakage path, one needs to increase the gate-oxide thickness of the pull-down transistors. To reduce other (minor) tunneling gate leakage currents in the SRAM cell, one only needs to increase the gate oxide thickness of the pass transistors, because from the previous discussion, it can be concluded that the gate leakage saving achieved by increasing the oxide thickness of the pMOS transistors would be quite small. Increasing the oxide thickness of a transistor not only increases the threshold voltage, but also reduces the drive current of the transistor. So, the effect of applying this technique to an SRAM cell is an increase in the read/write delay of the cell. This is general equation for leakage in SRAM cell that govern all leakage in TCAM memory.

1. Conventional Cell16T TCAM

   Fig. 2. shows the leakage paths in a 6T-SRAM-based TCAM cell when the BLs are charged to the mask state (BL1 = BL2 = 0), and minimum-size transistors are used. ISN and ISP are NMOS and PMOS subthreshold leakages respectively. NMOS gate leakages are specified by IGON and IGOFF for ON and OFF transistors, respectively. Similarly IGONP and IGOFFP are PMOS gate leakages.

   Leakage Current	Measured Current	Modified Value (fA)
   2ISN	2(-4.9087 n+ 802.77f)	-9.815 e6 f
   2ISP	2(6.0318 u + 3.6117 u)	19.287 e9 f
   2IGON	2(-1.8082 f + 4.998 e-16 A)	-2.6168 f
   6IGOFF	6(1.3378 e-17 A+ -2.934 e – 17A)	-9.5772 e-2 f
   2IGONP	2(3.20 f + -1.089 e -16 A)	6.1822 f
   2IGOFFPK	2(-9.2001 e-16A + 3.6729 e-16A)	-5.5272 e-1 f

   Assuming random data, a TCAM column with shared BLs has the same probability of storing 0, 1 and mask

   Larger transistors result in greater leakages. Since the READ speed is not critical in a TCAM, minimum size transistors can be USED.

   This choice also reduces the cell area. Conventional SRAMs also precharge BLs to VDD in order to perform fast READ operation.

   Fig. 2. Conventional TCAM Cell

   Leakage Current	Measured Current	Modified Value (fA)
   2ISN	2(-4.9087 n+ 802.77f)	-9.815 e6 f
   2ISP	2(6.0318 u + 3.6117 u)	19.287 e9 f
   2IGON	2(-1.8082 f + 4.998 e-16 A)	-2.6168 f
   6IGOFF	6(1.3378 e-17 A+ -2.934 e – 17A)	-9.5772 e-2 f
   2IGONP	2(3.20 f + -1.089 e -16 A)	6.1822
   2IGOFFPK	2(-9.2001 e-16A + 3.6729 e-16A)	-5.5272 e-1 f

   TABLE I

   LEAKAGE CURRENT OF CONVENTIONALJ TCAM

   Table I gives leakage current of different transistor of 16 T TCAM Cell. In TCAMs, BLs can be precharged to the state, which results in the minimum leakage. Figure 1 can be used to calculate the leakage current for a 6T- SRAM-based TCAM cell as given by equation (3) for different storage conditions. Below table shows abbreviations

2. NMOS-Coupled TCAM Cell

   Till this point we have studied conventional TCAM cell. In 2006, Nitin and Manoj [13] presented a novel ternary storage cell. In this paper we have review this NMOS and

   Next PMOS technique .Each TCAM cell contains two SRAM cells to store the ternary value. These SRAM cells can have four combinations: 00, 01, 10, and 11. Table II shows leakage current of NMOS coupled TCAM cell

   Leakage Current	Measured Current	Modified Value (fA)
   2ISN	2(-4.9087 n+ 802.77f)	-9.815 e6 f
   2ISP	2(6.0318 u + 3.6117 u)	19.287 e9 f
   2IGON	2(-1.8082 f + 4.998 e-16 A)	-2.6168 f
   6IGOFF	6(1.3378 e-17 A+ -2.934 e -17A)	-9.5772 e-2 f
   2IGONP	2(3.20 f + -1.089 e -16 A)	6.1822 f
   2IGOFFPK	2(-9.2001 e-16A + 3.6729 e-16A)	-5.5272 e-1 f

   TABLE II

   LEAKAGE AT NMOS COUPLED TCAM

   . However, only three out of them are used for the ternary value, and the unused state (typically 11) is forbidden. This ternary storage cell trades this unused state for a smaller leakage by coupling two 5T-SRAM cells and eliminating a subthreshold leakage path [13]. Fig. 3 shows the leakage paths of the NMOS-coupled (NC) ternary storage cell that connects two 5T-SRAM cells . For storing a ternary 0 or 1, one of the storage nodes (connected to the access transistors) is held at logic 0through the coupling NMOS transistor. Likely when the mask state is stored, both coupling NMOS transistors are OFF. Note that when both coupling NMOS transistors are ON, the cell is not stable. Hence, this cell can store only three states. It can be noticed in Figure 3. that the proposed cell can store only three states because the coupling does not allow the unused state. The total leakage current for an NC-TCAM cell (with BLs = mask) can be given by equation (5)

   INC_MASK/BLs=Mask = 2ISN + 2ISP + 2IGON + 6IGOFF + 2IGONP + 2IGOFFP (6)

   Thus, it will exhibit less leakage than the 5TSRAM- based cell only if condition (7) is satisfied:

   0.67ISN > 3.33IGOF F ISN > 5IGOFF (7)

   Fig. 3. NMOS Coupled TCAM Cell

3. P-MOS Coupled TCAM Cell

The coupling between the two 5T-SRAM cells can also be obtained by PMOS transistors. Fig. 4. shows the leakage paths of the PMOS-coupled (PC) TCAM cell. Similar to the NC-TCAM cell, one of the coupling PMOS transistors does not consume subthreshold leakage under 0 and 1 conditions. Thus, it will also exhibit smaller leakage than the 5T-SRAM-based cell if the subthreshold leakage is more than the gate leakage. The total leakage current for a PC-TCAM cell (with BLs set to the mask condition) can be given by equation (6).

IPC_MASK/BLs=Mask = 2ISN + 2ISP + 2IGON + 2IGOFF + 2IGONP

+ 2IGOFFP (8)

Similar to the 5T-SRAM-based cell, this BL precharge condition reduces both subthreshold and gate leakages. The PC-TCAM cell will consume less leakage than the 6T- SRAM-based cell only if condition (9) is satisfied.

0.67ISP > 0.67IGOFFP ISP > IGOFFP (9)

Similarly, the PC-TCAM cell will consume less leakage than the NC-TCAM cell (when BLs = mask) only if condition (10) is satisfied.

0.67ISP + 3.33IGOFF > 0.67ISN + 0.67IGOFFP ISP +

5IGOFF > ISN + IGOFFP (10)

Table III gives leakage current of PMOS coupled TCAM cell

TABLE IV

LEAKAGE CURRENT OF TCAM WHEN BITLINE=MASK

TABLE III

LEAKAGE AT PMOS COUPLED TCAM

If the gate leakage is comparable to the subthreshold leakage (ISN < 3IGOFF) and BLs of NCTCAM are at GND, the PC-TCAM cell will consume less leakage than the NC-TCAM cell if condition (10) is satisfied.

0.67ISP + 1.33IGOFF > 0.67IGOFFP ISP + 2IGOFF > IGOFFP (11)

Most CMOS processes will satisfy condition (8) because the PMOS subthreshold leakage and the NMOS gate leakage both are typically larger than the PMOS gate leakage.

The leakages of the above cells (when BLs = mask) are summarized in Table IV. It can be shown that that the 6T- SRAM-based cell always consumes more leakage than the other three cells

Fig . 4. PMOS Coupled TCAM Cell

.

III SIMULATION RESULT

We simulated the above TCAM cells using 0.35 µm technology. Figure 5 shows the leakage of different TCAM cells at 0.35µm CMOS technologies. It can be noticed that the magnitudes of different leakage components are related as follows:

ISN > ISP >> IGON > IGOFF >> IGONP > IGOFFP

Fig. 5. TCAM Cell Leakage for 35 nm CMOS technology

In this writing 1 was more difficult than writing 0 as it is tough to transfer 1 from NMOS transistor. The conventional 16 transistor TCAM area consume most area and hence most power dissipation. Newer approach like NMOS and PMOS use less area as number of transistor is less as well less power dissipation.

IV CONCLUSION

In this work we have studied and analyzed TCAM circuits with an emphasis on high capacity RAM. We have simulated conventional 16 transistor TCAM cell, NMOS coupled TCAM cell and PMOS coupled TCAM cell for low leakage andless area. Simulation results shows a reduction of up to 38% leakage reduction in NMOS and PMOS coupled TCAM cell as compared to conventional TCAM cell. The efficiency of PMOS coupled TCAM cell is best in all category

ACKNOWLEDGMENT

This work has been performed on Mentor-Graphics Tools at VLSI Design Lab, Department of Electronics and Communication Engineering, Guru Jambheswar University of Science and Technology, Hisar-125001

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