Harmonics analysis on asymmetric hybrid multilevel inverter based induction motor drive

Harmonics analysis on asymmetric hybrid multilevel inverter based induction motor drive

MR.K.KALAISELVAN. M.E.,

kalai123selvan@gmail.com / 8015329133 Dr.N.N.C.E.,

AbstractMultilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. This paper presents the most important topologies based harmonies cascaded multi cell with separate dc sources. Emerging topologies like asymmetric hybrid cells and soft-switched multilevel inverters are also discussed. Special attention is dedicated to the latest and more relevant applications of these converters such as laminators, conveyor belts, and unified power-flow controllers. The need of an active front end at the input side for those inverters supplying regenerative loads is also discussed, and the circuit topology options are also presented. This paper deals with performance of voltage source multilevel inverter-fed induction motor drive. A Voltage source inverter (VSI) is compared with multilevel inverter. A conventional Voltage Source Inverter-fed induction motor drive is modelled and simulated using Matlabsimulink and the results are presented. The FFT spectrum for the outputs is analyzed to study the reduction in harmonics.

Index TermsMedium-voltage drives, multilevel inverter.

1. INTRODUCTION

   In recent years, industry has begun todemand higherpower equipment, which now reaches the megawatt level.Controlled ac drives in the megawatt range are usually connectedto the medium-voltage network. Today, it is hard to connecta single power semiconductor switch directly to mediumvoltagegrids (2.3, 3.3, 4.16, or 6.9 kV). For these reasons, anew family of multilevel inverters has emerged as the solutionfor working with higher voltage levels. Multilevel inverters include an array of power semiconductorsand capacitor voltage sources, the output of whichgenerate voltages with stepped waveforms. The commutationof the switches permits the addition of the capacitor voltages,which reach high voltage at the output, while the powersemiconductors must withstand only reduced voltages. Fig. 1shows a schematic diagram of one phase leg of inverters withdifferent numbers of levels, for which the action of the power

   Fig. 1.One phase leg of an inverter with (a) two levels, (b) three levels, and (c) n levels.

   semiconductors is represented by an ideal switch with several positions. A two-level inverter generates an output voltage with two values (levels) with respect to the negative terminal of the capacitor [see Fig. 1(a)], while the three- level inverter generates three voltages, and so on.

   Considering that m is the number of steps of the phase voltage with respect to the negative terminal of the inverter, then the number of steps in the voltage between two phases of the load k is

   K=2m+1 1

   and the number of steps p in the phase voltage of a three-phase load in wye connection is

   p=2m-1 2

   The term multilevel starts with the three-level inverter introduced by Nabaeet al. By increasing the number of levels in the inverter, the output voltages have more steps generating a staircase waveform, which has a reduced harmonic distortion. However, a high number of levels increases the control complexity and introduces voltage imbalance problems. Three different topologies have been proposed for multilevel inverters: diode-clamped (neutral-clamped) capacitor-clamped (flying capacitors)and cascaded multicell with separate dc sources [1], The most attractive features of multilevel inverters are as follows.

   1. They can generate output voltages with

      extremely low distortion and lower dv

      dt

   2. They draw input current with very low distortion.

   3. They generate smaller common-mode (CM) voltage, thusreducing the stress in the motor bearings. In addition,using sophisticated modulation methods, CM voltagescan be eliminated [8].

   4. They can operate with a lower switching frequency.

   The results of a patent search show that multilevel inverter circuits have been around for more than 25 years. An early traceable patent appeared in 1975, in which the cascade inverter was first defined with a format that connects separately dc-sourced full-bridge cells in series to synthesize a staircase ac output voltage. Through manipulation of the cascade inverter, with diodes blocking the sources, the diode- clamped multilevel inverter was then derived .

   The diode-clamped inverterwas also called the neutral-point clamped (NPC) inverter when it was first used in a three-level inverter in which the mid-voltage level was defined as the neutral point. Because the NPC inverter effectively doubles the device voltage level without requiring precise voltage matching, the circuit topology prevailed in the 1980s. The application of the NPC inverter and its extension to multilevel converter was found in literature. Although the cascade inverter was invented earlier, its applications did not prevail until the mid1990s. Two major patents were filed to indicate the superiority of cascade inverters for motor drive and utility applications. Due to the great demand of medium-voltage high-power inverters, the cascade inverter has drawn tremendous interest ever since. Several patents were found for the use of cascade inverters in regenerative-type motor drive applications.

   The last entry for U.S. multilevel inverter patents, which were defined as the capacitor- clamped multilevel inverters, came in the 1990s Today, multilevel inverters are extensively used in high-power applications with medium voltage levels.

   The field applications include use in laminators, mills, conveyors, pumps, fans, blowers, compressors, and so on. This paper presents state-of-the-art multilevel technology, considering well-established and emerging topologies as well as their modulation and

   control techniques. Special attention is dedicated to the latest and more relevant industrial applications of these converters.

   Finally, the possibilities for future development are addressed.

2. THE INVERTER

   1. Power Circuit

      The power circuit of the Asymmetric Cascaded H-Bridge Inverter is illustrated in

      Fig. 2. The inverter is composed by the series connection of two or more H-bridge inverters

      (output levels:-Vdc , 0 and +Vdc, the optimal asymmetry is obtained by using voltage sources scaled proportional to the power of three. Applying this criteria to the voltage sources illustrated in Fig. 2, optimal design leads to

      [Vil, Vi2 . Vim]T

      = [30, 3l . 3(m-l)]T for phase i=a,b,c and m the number of cells per phase.

   2. Output Voltage Generation

   Since the power cells are connected in series, the total phase voltages generated by the inverter can be expressed as

   fed by independent dc-sources provided by m m

   individual secondaries of a transformer or

   ViN = L Vij = L Vij(Sjl – Sj2) i {a, b, c}

   batteries (if used in electric or hybrid vehicles

   j=l

   j=l

   for example). These sources are not equal, i.e.Vi1<Vi2<Vim for each phase i=a,b,c

   Fig 2 Asymmetric cascaded H-bridge multilevel inverter.

   The use of asymmetric input voltages can reduce, or when properly chosen, eliminate redundant output levels, maximizing the number of different levels generated by the inverter. Therefore this topology can achieve the same output voltage quality with less number of semiconductors. This also reduces volume, costs, losses and improves reliability. When cascading three level inverters like H-bidges

   Where ViN is the total output voltage of phase (respectively, the neutral of the inverter N),Vij is the output voltage of cell j of phase i, and (Sj1,Sj2) the switching state associated to cell j. Note how the output voltage of one cell Vij is defined by one ofthe four binary combinations of the switching state, with 1 and 0 representing the On and Off states of the corresponding switch, respectively. The voltage levels generated by the inverter can be calculated by replacing (1) into (2), and considering all the possible combinations of the switching states.

   The inverter generates 3m different voltage levels (e.g. an inverter with m=4 cells can generate 34=81 different voltage levels). When using three-phase systems, the number of different voltage vectors is given by 3.nl.(nl-1)+1 where nl is the number of levels. For example, for the case with 81 levels there are 19.441 different voltage vectors (huge difference compared to the nine levels and 217 vectors obtained with a 4- cell symmetric-fed cascaded inverter)

   Table I summarizes the output levels for an asymmetric ninelevel inverter using only m=2 cells per phase (only phase is given). An example of the voltage waveform generation for an asymmetric nine-level inverter is illustrated in Fig. 3

   Fig.2. Output voltage generation with asymmetric inverter..

3. Simulation Result

   The method was tested using an 27-level asymmetric inverter-fed induction motor drive. The inverter simulation diagram is shown in Fig.3 and the motor parameters are given in Table II.

   Table II Motor Parameter

   TABLE I

   NINE-LEVEL ASYMMETRIC CASCADED INVERTER SWITCHING STATES

   Paramete r	RS	LS H	Rr	Lr	Lm
   Value	0.43 5	0.00 2	0.43 5	0.00 2	69.31e -3
   Paramete r	J	F	P	Normal power
   Value	0.08 9	0.00 5	2	2238

   Conn1 Conn2

   + v

   –

   double

   Voltage M

   double

   Induction machine

   double

   d<oRuobtleor speed (wm)>

   #	Cell1			Cell 2			Total
   	S11	S12	Va1	S21	S22	Va2	VaN
   1.	1	0	Vdc	1	0	3 Vdc	4 Vdc
   2.	0(1)	0(1)	0	1	0	3 Vdc	3 Vdc
   3.	0	1	– Vdc	1	0	3 Vdc	2 Vdc
   4.	1	0	Vdc	0(1)	0(1)	0	Vdc
   5.	0(1)	0(1)	0	0(1)	0(1)	0	0
   6.	0	1	– Vdc	1(0)	1(0)	0	– Vdc
   7.	1	0	Vdc	0	1	-3 Vdc	-2 Vdc
   8.	1(0)	1(0)	0	0	1	-3 Vdc	-3 Vdc
   9.	0	1	– Vdc	0	1	-3 Vdc	-4 Vdc

   powergui

   Subsystem Step Tm

   Discrete, s = 5e-006 s

   A

   Conn1 B

   Conn2 C

   Subsystem1

   d<oEulbelcetromagnetic torque Te (N*m)> d<oRuobtleor angle thetam (rad)> d<oSutbalteor current is_a (A)>

   m d<oSutbalteor current is_b (A)>

   <Stator current is_c (A)>

   double

   Conn1

   Conn2

   + v d

   –

   Vol

   ouble

   Subsystem2

   + double

   v

   –

   Volta

   double

   Scope6

   Fig3 :Simulation diagram

   Simulation diagram of 27-levelasymmetrical multilevel inverter three phase inverter fed induction motor drive is shown in Fig.3. The

   induction motor is fed from 27-level inverter. The circuit of 27-level inverter is single phase simulation leg is shown in Fig. 4.

   The output voltage waveforms of the inverter are shown in Fig.5. The stator current waveforms are shown in Fig. 6.

   Speed response of the induction motor drive is shown in Fig.7. The rotor speed increases and settles at1470 rpm.

   The frequency spectrum for the output of 27- level inverter is shown in Fig.8. The THD in 27- level inverter is found to be 9.80

   g

   C

   g

   C

   double

   Fig5 output voltage waveform

   E

   double

   double

   double

   double

   double

   g

   C

   E

   DC 1

   DC 2

   E

   g

   C

   E

   DC 3

   Se2

   Se

   g

   C

   g

   C

   g

   C

   E

   g

   C

   E

   Se1

   g

   C

   g

   C

   E

   2 Conn2

   E

   g

   C

   E

   1 Conn1

   E

   Fig 6 stator current waveform

   g

   C

   E

   E

   Fig 7 Motor speed response

   Fig4 simulation diagram of single phase

   Fig 8 FFT analysis of eleven level

4. Conclusion

   This paper has provided a cascaded multilevel inverter can be traced back to 1975. However,the commercial products that utilize this superior circuit topology were not available until the mid-1990s. Today, more and more commercial products are based on the multilevel inverter structure, and more and more worldwide research and development of multilevel inverter- related technologies is occurring. This paper cannot cover or reference all the related work, but the fundamental principle of asymmetrical multilevel inverters has been introduced systematically. The results of multilevel inverter systems are compared with the results of VSI based drive system.

   It is observed that the total harmonic distortion produced by the 27-level inverter system is less than that of a 9-level VSI fed drive system. Therefore the heating due to 27-level inverter system is less than that of a 9-level VSI fed drive system. The simulation results of voltage, current, speed and spectrum are presented. This drive system can be used in industries where adjustable speed drives are required to produce output with reduced harmonic content. The scope of this work is the modeling and

   simulation of 27-level and 9- level inverter and VSI fed induction motor drive systems. Experimental investigations will be done in future.

5. REFERENCES

1. Bashi, S.M., N. Mariun and N.F. Alhalali, 2008. On low harmonic single phase multilevel power inverter. Asian J. Sci. Res., 1(3): 274-280.

2. Dixon, J. and L. Moran, 2006. High-level multi-step inverter optimization using a minimum number of power transistors. IEEE Tran. Power Electron., 21(2):

   330-337.

3. DuLeon, Z., M. Tolbert and J.N. Chiasson, 2006. Active Harmonic Elimination for Multilevel Converters. IEEE Tran. Power Electron., 21(2): 459-469.

4. Feng, C. and G.A. Vassilios, 2000. On the Comparison of fundamental and high frequency Carrier based techniques for multilevel NPC Inverters. IEEE PES Conf., 2: 520-525.

5. Golubev, A.N. and S.V. Ignatenko, 2000. Influence of number of stator winding phases on noise characteristic of an asynchronous motor. Russ. Electr. Eng., 71(6): 41-46.

6. Gopukumar, K., S.K. Biswas, S. Satishkumar and V. Joseph 1984. Modified current sourceinverterfed induction motor drive with reduced torque pulsation. IEE Proc., 313(4): 150-164.