Design of A Pipeline for A Fixed-Point Multiplication using Single Electron Tunneling Technology

Design of A Pipeline for A Fixed-Point Multiplication using Single Electron Tunneling Technology

Anup Kumar Biswas

Assistant Professor, Department of Computer Science and Engineering Kalyani Govt. Engineering College, Kalyani,

Nadia-741235, West Bengal, India,

Abstract:- For high operating speed, low power consumption, and high integration density-based equipment(s) are financially indispensable in engineering, science and technology in the present era. Single Electron tunneling Device (SED) is one such equipment by which all Boolean logic gates can be implemented. SEDs and Linear Tunnel Gates (TLG) are capable of controlling the transport of only an electron through the tunneling junction. It is a single electron that is sufficient to store information in the SED in the atmosphere of 0K. Power consumed in the single electron tunneling circuits is very low in comparison with (CMOS) circuits. The processing speed of TLG based device will be nearly close to electronic speed. The single-electron transistor (SET) and LTG attracts the researchers, scientists or technologists to design and implement large scale circuits for the sake of the consumption of ultra-low power and its small size. All the tunneling events for the case of a LTG-based circuit happen when only a single electron tunnels through the tunnel junction under the proper applied bias voltage and multiple input voltages. For implementing a fixed-point Multiplication circuit, LTG would be a best candidate to fulfil the requirements of it. Ultra-low noise is generated during tunneling through the LTG based circuit. Different logic gates, a D-Flip-flop, a full adder are implemented, and based on them, a Pipeline for a fixed-point Multiplication is presented at last.

Key words: Electron-tunneling, Coulomb-blockade, pipeline, Multiplication, linear threshold gate

1. COULOMB BLOCKADE AND SINGLE ELECTRON TRANSISTOR

   A tunnel junction in Fig.1 (a) comprises a thin insulating barrier between the two conducting electrodes It is having a capacitance C and a resistance . The electrodes of the tunnel junction may be a superconducting or semiconducting. If they are of superconducting, electrons with one elementary charge (1.602×1019 C) carry the current.

   In the classical electrodynamics, current cant flow through the insulating barrier. But in the case of quantum mechanics, there must be a positive probability (i.e., more than zero) for an electron residing one side of the barrier to reach the other side of it when the proper bias or input voltages are supplied. If bias voltage is applied properly, there will be a current flow. Neglecting other effects, in accordance with first-orderapproximation-tunneling, current will be following in proportion to the applied bias voltage. In the case of electrical terms, a tunnel junction shown in Fig 1(a) behaves as a resistor having a constant value depending on its barrier thickness. If two conductors are connected with an insulating layer between them, there will have not only a resistance but also a capacitance in the junction. In this context, the insulator acts as dielectric and two conducting plates with dielectric forms a capacitor in the tunnel junction. For the discrete nature of electric charge, current following through a tunnel junction is a series of events in which merely one electron will be able to pass or tunnel through the tunnel junction. If the single electron tunnels the junction, the tunnel capacitance is charged with an elementary charge (1.602 × 1019 C) building up a

   voltage V= , where C=junction capacitance. When the capacitance of the tunnel junction is ultra-small, the voltage building up

   in the tunnel junction may be adequate to prevent another electron to pass through. The electrical current is suppressed as the bias

   voltage is lower than the voltage created in the tunnel junction and the resistance of the device will no longer remain constant. The increment of the differential resistance of the tunnel junction around zero bias is called the Coulomb blockade [3, 10, 13, 17].

   Fig.1 (a) Tunnel Junction Fig.1 (b) Single Electron Transistor (SET)

   The principle of single-electron technology [2, 3, 4, 9, 16] is developed on the basis of the single electron tunneling and Coulomb blockade. Single electron tunneling circuits seems to be a promising candidate for future VLSI circuits for its ultra-low power consumption, ultra-small size, reducing node capability and rich functionality.

   A (SET) [4, 5] made up of two tunnel junctions shown in Fig. 1(b) having their capacitances and resistances 1, 2 and 1, 2 respectively, shares only a common inland with a low capacitance. The electric potential of the island can be tuned in by a third electrode, called gate, and the gate is capacitively coupled (gate capacitance ) to the island. An extra capacitance 1 may intentionally be connected to the island for the purpose of manipulating the gate voltage (input). The drain, source and gate voltages are marked by , and respectively. For proper operations of SET both of the resistances 1, and 2, are to be greater than = h/ 2 25.8 K and charging energy EC=e2/2C [where = 1 + 2+ + 1] has to be greater than thermal

   fluctuations , i.e,

   = > , the product of the Boltzmann constant, k , and the temperature, T in kelvin. The Boltzmann

   2

   2

   2

   constant value is 1.380649 × 1023 joule / kelvin , or 1.380649 × 1016 erg / kelvin.

2. INVERTER

   The inverter [3, 7, 8] depicted in Fig. 2(a) is made up of two SETs connected in series. The same input voltage is directly coupled to the islands of the SET1 and SET2 through two capacitors 1 and 2 respectively. The island of each SET has a size smaller than 10 nm of gold and their capacitances must be less than 10-17 F. The output terminal 0 is connected to the common channel of the two SETs and to the ground via a capacitor to put down charging effects.

   Fig.2 (a) an Inverter Fig.2 (b) Symbol of an Inverter

   For the inverter, the parameters values chosen are:

   =0,

   =0.1× ,

   = 9, = 1 , = 1 , = 1 ,

   = 1 , =

   1

   2

   4 10 3 2 2 2

   1 10 1

   1 ,

   = 1 ,

   = 17 and

   = 17 , R1 =R2=100K. For simulation purpose, the value of C is taken 1aF.

   2 2 2

   1 4

   2 4

   The operation of the inverter will be like this: – the output 0 value will be high when the input voltage Vin is low and 0 value will be low when the input voltage is high. For achieving this target, we set the voltages 1 = 0 2 =16mV along with the tuning gate voltages, at present, Vin both for SET1 and SET2. Now if is low, the SET1 is in conduction mode and the SET2 is in Coulomb blockade. This effectively results the output to voltage and causes the output voltage to be high, Coulomb blockade interferes the steady flow of current because whenever the high voltage (logic 1) is applied to the input, it causes to shift the induced charge on each of the islands of the two SETs by a fraction of an electron charge and keeps the SET1 in Coulomb blockade and the SET2 in conducting mode. As a result, the output shifts from high to low.

   Fig. 2(c) Simulation set of Inverter Fig.2 (d) Simulation result of Inverter

   In this work we assume the Boolean logic inputs corresponding to the voltages like: logic 0 =0 Volts and logic 1=0.1×

   19

   19

   We assume, for simulation and other purposes, C=1aF then Logic 1= 0.1× 1.602×10 =0.1 × 1.602 × 102=16.02 ×

   11018

   103 =16.02 16 mV.

3. MULTIPLE INPUT THRESHOLD LOGIC GATE

   The multiple input threshold logic gate [5, 7, 8, 14] consists of a tunnel junction, two multiple inputs connected at points a and b. Each input voltage , for the upper side is

   connected to point b through the capacitor and each input voltage , for the lower

   side is connected to point a through the capacitor . Bias voltage is also connected to point b through a capacitor . Point a is grounded through a capacitor 0 . The capacitor of tunnel junction is . This multiple input threshold logic gate can also be

   defined as a Junction-Capacitor (C-J) circuit. Using the Junction-Capacitor circuit we will be able to implement the linear threshold gate (LTG) being presented by the signum function of g(x) expressed by equations (3) and (4).

   f(x) = sgn{g(x)} = { 0, () < 0

   1, () 0

   … (3)

   =

   =

   g(x)= 1( × ) – ..(4)

   =

   =

   where are being the n Boolean inputs and are being the corresponding n integer weights. The linear threshold gate compares the weighted sum of the inputs 1( ×

   ) with the threshold value . If the value of the weighted sum is greater than the

   Fig. 3 Multiple input threshold logic gate

   threshold or critical voltage value then the logic output of the LTG will be 1, otherwise it will be 0.

   The tunnel junction capacitance and the output capacitance 0 are considered the two basic circuit elements in a LTG. The input signal vector elements { , , , , } are weighted by their respective vector element capacitances

   1 2 3

   {, , , , } and added to the voltage, , across the tunnel junction. On the other hand, the input signal vector elements

   1 2 3

   { , , , , } are weighted by their respective vector element capacitances {, , , , } are being subtracted from

   1 2 3 1 2 3

   the voltage, , across the junction.

   The critical voltage required to enable tunneling action, and it acts as the intrinsic threshold of the tunnel junction circuit. The bias voltage connected to tunnel junction through the capacitance, , is really being used to adjust the gate threshold to the desired value . When a tunneling phenomenon happens though the tunnel junction an electron passes through the junction from a to b [Fig. 3].

   +

   +

   C

   C

   We are using the following notations for the rest our discussion.

   CP = Cb

   g P

   k=1 k

   …(5)

   Cn = C0 + h

   Cn . (6)

   l=1 l

   = CP + CPCn + Cn. (7)

   When we are thinking of all voltage sources in Fig. 3 to be 0 (or connected to ground), the circuit can be thought of three capacitors connected in series, namely CP, Cn and . Here, is represented by the sum of all 2-term products of these three capacitances.

   It is the time to find the expression of critical voltage of the tunnel junction. We suppose the capacitance of the tunnel junction being and the remainder of the circuit having the equivalent capacitance is , as observed from the tunnel junctions perspective, we can measure the critical voltage[6,7] for the tunnel junction as

   = 0.5

   .. (8)

   +

   = 0.5 + (||) = 0.5

   ( ) ()

   +

   ( + )

   ( + )

   = 0.5

   ( + ) + ( ) ()

   (+)

   = 0.5

   .. (9)

   When we define the voltage across the junction as , a tunnel event will happen through this tunnel junction if and only if the following condition is satisfied.

   || (10)

   If the junction voltage is less than the critical voltage i.e. || < there being no tunneling events through the circuits tunnel junction. As a result, the tunneling circuit remains in a .

   Theoretically, the thresholds are being integer numbers. And the threshold logic equations for two inputs AND, OR, NAND and NOR gates can be written [6] as follows.

   (, ) = { + 2} (11)

   (, ) = { + 1} (12)

   (, ) = { + 2} (13)

   (, ) = { + 1} (14)

   If the threshold becomes = (i being an integer value), this implies that the gates perform their functions correctly for any value in the interval [ 1 < ]. For the purpose of maximizing robustness for variations in parameter values, the threshold value = is replaced by the average = 0.5. As a result, the threshold logic equations for the two-input AND, OR, NAND and NOR gates can be expressed as

   (, ) = { + 1.5} (15)

   (, ) = { + 0.5} (16)

   (, ) = { + 1.5} (17)

   (, ) = { + 0.5} (18)

   The threshold gate-based implementations of the Boolean Logic gates have the same basic circuit topology for all we have to draw in the subsequent sections. The threshold gates consist of a bias capacitance , a tunnel junction having capacitance , and an output capacitance 0 . The AND and OR gates contain two input capacitors. For both the and gates, the two

   input capacitors are CP = CP = 0.5 for positively weighted inputs. On the other hand, for the NAND and NOR gates, two

   1 2

   capacitors hold the values as Cn = Cn = 0.5 for negatively weighted inputs.

   1 2

   Every threshold gates is augmented with an inverter/buffer. The function of the inverter/buffer is to invert the input of a threshold gate. The logic function done by the buffered threshold gate is being the inverse of which is done by the threshold gate itself. For instance, a buffered gate implements the function. For the rest of our discussion, when we refer to a logic function such as AND, we imply the logic function performed by the entire gate (i.e., threshold gate plus an output buffer).

   The parameters used for the implementations and simulations of different gates like AND, OR, NAND and NOR gates and other combinational or sequential circuits are given in Table-1 [6,7].

   Table-1

   Threshold gate

   Cb

   C0

   CP 1

   Cp 2

   Cn 1

   Cn 2

   Cg1 = Cg2

   C2 = C3

   C1 = C4

   Cb1 = Cb2

   CL

   2-inout AND

   10.6C

   8C

   –

   –

   0.5C

   0.5C

   0.1C

   0.5C

   0.1C

   0.5C

   4.25C

   9C

   2-inout OR

   11.7C

   8C

   –

   –

   0.5C

   0.5C

   0.1C

   0.5C

   0.1C

   0.5C

   4.25C

   9C

   2-inout NAND

   13.2C

   9C

   0.5C

   0.5C

   –

   –

   0.1C

   0.5C

   0.1C

   0.5C

   4.25C

   9C

   2-inout NOR

   11.7C

   9C

   0.5C

   0.5C

   –

   –

   0.1C

   0.5C

   0.1C

   0.5C

   4.25C

   9C

   3-inout OR

   11.8C

   7.8C

   0.4C

   –

   0.5C

   0.1C

   0.5C

   0.1C

   0.5C

   4.25C

   9C

   0 = 0 , 1 = 16 , =105 , =0.1aF, other capacitance values are in terms of , where = 1

4. AND GATE

   For implementing the AND gate we will use the parameters = =0.5aF, = = 4.25, 1 = 2 =

   1 2

   0.5, = 9, 0 = 8, =105 in Fig. 4(a) and accordingly after running the simulator the output we

   get is given in Fig. 4(b).

   Fig.4 (a) AND Gate Fig.4 (b) Simulation result of AND gate

5. NAND GATE

   For implementing the NAND gate, we will use the parameters = =0.5aF, = = 4.25, 1 = 2 =

   1 2

   0.5, = 3 = 13.2, = 9, 0 = 8, =105 in Fig. 5(a) and accordingly after running the

   simulator the output we get is given in Fig.5(b).

   Fig.5 (a) NAND Gate Fig.5 (b) Simulation result of NAND gate

6. OR GATE

   For implementing the OR gate we will use the parameters = =0.5aF,3 = 11.7, = = 4.25,

   1 2

   1 = 2 = 0.5, = 9, 0 = 8, =105 , = 16 and accordingly after running the simulator the

   output we get is given in Fig. 6(b).

   Fig. 6(a) OR gate Fig. 6(b) simulation result of OR gate

7. EXCLUSIVE OR (XOR) GATE

   For implementing the XOR gate we will use the parameters = =CP = CP = = 0.5aF, 3 = 11.7,

   1 2 1 2

   = = = 4.25, 1 = 2 = 0.5, = 9, 0 = 8, = 0.1aF, = 105 , = 16 and

   accordingly after running the simulator the output we get is given in Fig. 7(b).

   Fig. 7(a) XOR gate Fig. 7(b) simulation result of XOR gate

8. DESIGN OF D-FLIP-FLOP USING LOGIC GATES

   The flip-flop is a sequential circuit used for storing data from two stable states. A classical D Flip-flop is consisting of four NAND gates and one inverter shown in Fig. 8(a). There are two inputs- D and Clock, and two outputs- Q and Q . The input output relationship is shown in the truth table in Fig. 8(b).

   Truth table
   Clock	D	Q
   0	0 or 1	No Change
   	0	0
   	1	1

   Truth table
   Clock	D	Q
   0	0 or 1	No Change
   	0	0
   	1	1

   Fig. 8(a) Diagram of D-flip flop Fig. 8(b) Truth table.

   On the basis of the pattern of the D Flip-flop drawn in Fig. 8(a), we can easily implement a D Flip-flop with the help of threshold logic gate based NAND and a buffer/ inverter shown in Fig. 2(a) or 2(c).

   The same parameters used in the case of a NAND and an inverter will be used in the TLG-based D Flip-flop. The output is provided with the positive edge trigger of the clock.

   The input and output signals of the D-Flip-flop shown in the Fig. 9(b) through 9(e) are the D-Flip-flop input signal, Clock signals, output of the Q and output of Q respectively.

   Fig. 9 (a) D Flip-flop using one buffer and four NAND gate based on TLG (b) D input (c) clock signal

   (d) output of Q and (e) output of Q

9. FULL ADDER

   The logical expressions of a full adder [7] for two inputs and with carry are: (i) sum and (ii) Carry +1 are given in equations (19) and (20) respectively.

   = .. (19)

   +1 = . (20)

   Fig.10 (a) A single bit Full Adder

   Fig. 10(b) three inputs Fig. 10(c) sum & Carry output

   According to the equations (19) and (20), we have implemented a full adder circuit in Fig. 10(a). To implement the full adder circuit, it requires two XOR gates, three AND gates and two OR gates which have already been described. The simulation results are shown in Fig. 10(b) and 10(c). Solution space of the full adder having two Boolean expressions of = ( ) = 1 and carry out +1 = ( ) =1 is represented by the Fig. 10(d).

   Fig. 10(d) Solution space of = ( ) = 1 Black color, and Solution space of +1 = ( ) =1 Red color

10. CARRY PROPAGATION ADDER

    Fig.11 (a) A sixteen-bit Carry-propagate Adder (CPA), (b) Sum of A and B, (c) Symbol of sixteen-bit CPA

    For the purpose of high-speed operation of addition, the use of Carry-propagation adder (CPA) [19] is needed. The CPA adds two binary numbers of 16-bits and produces an arithmetic sum depicted in Fig. 11(b). The carries generated in this case in successive digits are propagated from LSB end toward MSB end. The CPA can be created either by using ripple carry propagation or carry look-ahead technique. Here we have adopted the first case, i.e., ripple carry propagation. A figure of a CPA, an example of its calculation and the symbol of CPA are given in Fig.11 (a), (b) and (c) respectively.

11. CARRY-SAVE ADDER

    A separate high-speed addition technique will be required for adding three numbers at a time and we define this technique as Carry-save adder (CSA) [19]. In CSA the carries will not be allowed to propagate from low to high end but instead they will be saved in a carry vector representing a number. In a general way, an n-bit CSA is specified like this: We assume that A, B and C are three n-bit numbers expressed as A= (1, 2 , 1, 0 ,), B= (1, 2 , 1, 0 ,) and C = (1, 2 , 1, 0 ,).

    The CSA operations are performed bitwise simultaneously on a column of digits to generate two n-bit numbers as (i) sum vector

    = (0, 1, 2 , 1, 0 ) and carry vector C= (, 1 , 1, 0, 0), Noted that, the leading bit for the , of course, is a 0 and the tail bit for the carry vector C is a 0. Input-output relationship will be expressed by the equations given in (19) and (20), for i = 0, 1, 2, …, n-1, where indicates exclusive-OR and indicates logical OR operation.

    Now, after the addition of three binary numbers A, B and C we obtain the arithmetic sum =ABC. And is obtained by bit-wise addition of two binary numbers and carry shown in Fig. 12(c) i.e., = +. The operation of CSA is presented in Fig. 12(d) and its symbol is given in the Fig.12(e) .

    Fig.12 (a) Sum , (b) carry (c) bitwise sum , (d) n-bit CSA and (e) symbol of CSA

12. DESIGN OF A PIPELINE FOR A FIXED-POINT MULTIPLICATION

    The PCA and CSA discussed above will be used for implementing the Pipeline stages for a fixed-point Multiplication unit [19]. For the design purpose we consider an example of multiplication of two eight-bit integer numbers A and B and their product P=A×B, where P is a 16-bit number. The fixed-point multiplication can be treated as the sum of eight different partial products depicted in the Fig.13, where P = A×B = 7 + 6 + 5 + 4 +3 + 2 +1 + 0 , in this case × + arithmetic multiplication and addition operations.

    Fig. 13 Product P and partial products 0, 1, 2 , 3 , 4, 5, 6 and 7

    The partial product , = 0, 1, 2, ,7 is obtained after multiplying the multiplicand A by the -th bit of the multiplier B. Then we shift the result bits to the left for i = 0, 1, 2, … ,7. Thus, we obtain which is (8 + i) bits wide in length with trailing zeros. The summation of all the partial products starting from 0 to 7 is completed with a of some Carry-save adders (CSAs) and one CPA which is the final stage.

    Taking the generation vector of eight bits for the ases A and B, we assume A= (7, 6 , 5 , 4 , 3 , 2 , 1, 0 ), B = (7, 6 , 5 , 4 , 3 , 2 , 1, 0 ) and P = (7, 6, 5, 4 ,3, 2, 1, 0). With the help of the AND gate and D-Flip-flop, eight numbers of circuit shown from Fig.14 (a) to Fig.14 (h) have been implemented to generate partial products 7, 6, 5,4 , 3, 2, 1 and 0 with respect to (7, 6 , 5 , 4 , 3 , 2 , 1 0 ) and one bit from (7, 6 , 5 , 4 , 3 , 2 , 1 0 ) each time.

    With the help of circuits drawn like CPA, CSA, partial product-circuits for 0, 1, 2 , 3 , 4, 5, 6 and 7 and AND gates we have presented a pipeline bearing four stages and five switching circuits which are driven with the rising edge of clock pulse.

    In stage-1, all the required partial products 0, 1, 2 , 3 , 4, 5, 6 and 7 ranging from 8 bits to 15 bits simultaneously are generated by dint of the diagrams drawn in Fig.14(a) through Fig.14(h). The second stage (stage-2) is made up of two levels of four CSAs merges eight numbers ranging from 8 bits to 15 bits into four numbers ranging from 13 bits to 15 bits. The third stage (stage-3) comprising of two levels of two CSAs merges four numbers ranging from 13 bits to 15 bits into two numbers of 16 bits each. The fourth and final stage (stage-4) consisting of a CPA adds up the two 16 bits numbers to create the final value of 16 bits, the product of A and B, P=A×B.

    Fig.14 Partial product 0, 1, 2 , 3 , 4, 5, 6 and 7 circuits

    Fig.15 Pipeline for a fixed-point Multiplication

13. DISCUSSION

To find out the delay of a logic gate we require critical voltage which is given in equations (8) and (9), and tunnel junction capacitance . However, assuming at T = 0K, the switching delay of a logic gate can be calculated using the approach [6, 7].

Delay=|ln ( )|

||

..(21)

where is the junction voltage and is the critical (threshold) voltage

The slowest switching happens when the critical voltage becomes lesser than the tunnel junction voltage , < | |, but very near to it. This will happen, for example when only 1 is logic 1, resulting =11.8mV for 2-input NOR, the critical voltage of the tunnel junction voltage is 11.58mV. Given that the probability of error change =1012, = 100. We get a gate delay = 0.07281|ln ( )|ns = 1.675 ns. In the same way we can determine the circuit delays which have been written in Table-

1. When charge tunnels through the tunnel junction, the amount of total energy changes before and after the tunneling. So the

   difference in the amount of energy in the tunnel circuit before and after the tunneling event is determined by = =e(|| ) and it is the amount of switching energy consumed in a tunnel event in the tunneling circuit.

   We have depicted the switching delay as a function of the switching error probability in Fig. 16(a) and the switching delay as a function of the unit capacitance C is shown in Fig. 16(b).

   At first, we have found out the area/element numbers, switching delay, and switching energy consumption for the individual linear threshold gates (using the same methodology as adopted for the Boolean gates). Next, we have calculated the same parameters for more bigger and complex circuits and that are presented in Table-2.

   Gate	Area	Delay	Switching Energy
   inverter	09 elements	0.022|ln() | ns	10.4 meV
   2-input NOR	14 elements	0.072|ln( )| ns	10.7 meV
   2-input OR	14 elements	0.062|ln( )| ns	10.8 meV
   2-input NAND	14 elements	0.080|ln() |ns	10.7 meV
   2-input AND	14 elements	0.062|ln() |ns	10.8 meV
   2-input XOR	20 elements	0.102|ln( )| ns	21.2 meV
   D latch	65 elements	0.342|ln( )| ns	53.2meV
   Full Adder	40 for sum 70 for carry	0.204|ln( )| ns 0.186|ln( )| ns	42.4 meV 32.3 meV
   CSA	n×40 for sum n× 70 for carry	0.204|ln( )| ns 0.186|ln( )| ns	0.204n meV 0.186n meV
   CPA	240 for sum 280 for carry	3.264|ln() | ns 2.976|ln() | ns	678.4 meV 516.8 meV
   7	1087 elements	0.404|ln() | ns	884.4 meV

   Table-2

   Time delay for the stage-1 is 0.404|ln( )| ns, for stage-2 is 0.408|ln( )| ns, for stage-3 is 0.408|ln( )| ns, for stage-4 is 3.264|ln( ) | ns and for the switching circuit if we consider it as an AND gate then its delay time is 0.062|ln( ) |ns.

   Fig. 16(a) Delay Vs. Error Probability (b) Delay Vs. capacitance

   So the time delay to produce first output of product P=A×B for the case of a pipeline is equal to .

   = 0.404|ln() | + 0.408|ln( )| + 0.408|ln( )| + 3.264|ln() | + 5×0.062|ln() |

   =4.794 |ln( )| (ns)

   If we take the value of , for example, 1010 then the time required to produce output of product

   = 11.62ns (21)

   For the context of the pipeline, we are to consider worst case of delay for a stage of four stages in the present situation and this

   delay is calculated by equation (22)

   = max{0.404|ln() |, 0.408|ln( )|, 0.408|ln( )|, 3.264|ln() |} + 0.062|ln() |

   =3.326 |ln() |ns .(22) Therefore the output rate or frequency of the pipeline having stages four is

   = 1

   = 1

   3.326 |ln() |ns

   (23)

   = 1

   2.3025850929940

   If we take the value of , for example, 1010 then the output rate will be

   =0.434294× 109=434.294MHz…(24)

   From the equation (21) the first output of 16-bit product will be produced after 11.62ns and thereafter the output rate from equation (24) is 434.294MHz.

   1. COMPARISON OF SET AND TLG

      For a CMOS/TTL logic gate the time delay/processing delay for a gate like NAND, NOR, XOR is 12ns [20], on the contrary the time required for tunneling through a single electron transistor (SET) is approximately 4ns [4] [5]. The XOR gate using conventional logic circuits needs 16 transistors, whereas this function can be implemented with just one SET [1, 2, 4, 5, 10] i.e. number of nodes are reduced to 1 instead of 16. If the error probability is assumed to be 1015 then the delay for the inverter will be 2.3025ns and similarly the other delays for the other gates can be calculated as shown in Table-3. And it is clear that the TLG based circuit must be faster than the SET based circuit when = 1015.

      Table-3

      Circuit name	SET Circuit delay(ns)	TLG based circuit delays (ns)	TLG based circuit delays (ns) when = 1015
      Inverter	4×2=8	0.022|ln() |	2.3 ns
      NAND gate	4×4=16	0.080|ln() |	2.76 ns
      OR gate	4×1=4	0.062|ln( )|	2.14 ns
      XOR gate	4×1=4	0.102|ln( |	3.5 ns
      D-Flip-flop	16× 2=32	0.342|ln( )|	11.81 ns

   2. CONCLUSION

In this paper, first how an electron tunnels through a single electron transistor and an inverter is discussed. A generic Linear Threshold logic gate implementation from which we have derived a family of logic gates like AND, NAND, OR, NOR, XOR which are elaborately discussed. All the gates along with a full adder and a D Flip-flop are implemented and are verified by means of simulation using SIMON. The number of elements for logic gates, their delays, power consumed for them are also given in a tabular form. By dint of all these LTG gates and an inverter, a pipeline of complex circuit called Pipeline for a fixed-point Multiplication having four stages, has been presented. It is an 8 by 8 bit multiplication pipeline producing 16-bit output. Among the four stages, stage-4 takes more time to execute with respect to other three stages. In single electron tunneling technology the logic gates are at least 3 times faster than CMOS based logic gates. The atmosphere temperature should be close to 0K in real operation.

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   International Journal of Engineering, Science and Technology Vol. 1, No. 1, 2009, pp. 61-73

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BIOGRAPHY

Dr. Anup Kumar Biswas is an Assistant Professor in Commuter Science and Engineering in Kalyani Govt. Engineering College. He is awarded his PhD[Engg.] from Jadavpur University. He has engaged in teaching and research activities since the last 16 years. His Specialization field is Single Electron Device. Biswas has published several papers in various national, international conferences and journals.