Thin Film Fabrication And Characterization Of Inkjet Printed Nano Silver (AG) Interconnects

Thin Film Fabrication And Characterization Of Inkjet Printed Nano Silver (AG) Interconnects

1J. Cyril Robinson Azariah, 2P. Saravanan, 3C. Mohan Raj, 4A. Rahamathullah,

5T. Veeramani and 6R. Vikram Singh

1Assistant Professor, 2PG Scholar, 3-6UG Scholars, Department of Electronics and Communication Engineering,

V.S.B Engineering College, Karur, Tamilnadu, IN-639111.

ABSTRACT:

This work has resulted a promising replacement element, nano silver to overcome the present day interconnect issue and to meet the future requirements of circuit fabrication. Initially precursor Solution, Silver Nitrate (AgNO3), an environment friendly reducing agent tannic acid (C76H52O46), and chemicals Carboxy Methyl Cellulose Sodium Salt (C8H16NaO8), Sodium carbonate(Na2CO3) were all dissolved in appropriate volume of deionized water and these solutions were stirred for one hour protecting away from sunlight .The prepared solution was used as a conductive ink in a inkjet printer to draw interconnect pattern on the substrate. A thin film of nano silver Pattern remained on the substrate. SEM images and XRD analysis of thin film nano silver pattern were carried out and these patterns were characterized to prove its identity to find application as interconnect in ULSI technology.

Key words: Ag interconnects; Inkjet Printing; Moores Law; Thin Film; ULSI.

Corresponding Author: J.Cyril Robinson Azariah

1. INTRODUCTION

   In the world of digital fabrication, the race still continues between human expectation for better circuit performance and circuit scaling. To satisfy Moores prediction law and work it for the future, fabrication technology has evolved from Small Scale Integration (SSI) to Ultra Large Scale Integration (ULSI).Yet after all these evolutions interconnect issues remain a crippling factor limiting the overall performance of the circuit. Present day VLSI fabrication technology uses copper element as interconnect which struggle to find a place in for the future scaling technologies. Interconnect, as the name describes is a medium to inter-connect two or more devices on a chip. The function of an interconnect is to distribute clock and other signals to the various functional blocks of a CMOS integrated circuit and is utilized like a metronome to coordinate actions of circuits [1,2].

   These clock signals are particularly affected by technology scaling (Moore's law), in that long global interconnect lines become significantly more resistive as line dimensions are decreased. Finally, the control of any differences and uncertainty in the arrival times of the clock signals can severely limit the maximum performance of the entire system and create catastrophic race conditions in which an incorrect data signal may latch within a register. Novel structures are currently under development to ameliorate these issues and provide effective solutions [3-5].

   Table No.1: shows the resistivity and conductivity of several materials.

   The values are correct at 20 degrees Celsius.

   Material	(m) at 20 °C Resistivity	o (S/m) at 20 °C Conductivity
   Silver	1.59×108	6.30×107
   Copper	1.68×108	5.96×107
   Gold	2.44×108	4.10×107
   Aluminum	2.82×108	3.5×107
   Zinc	5.90×108	1.69×107
   Nickel	6.99×108	1.43×107
   Iron	1.0×107	1.00×107
   Lead	2.2×107	4.55×106

   1.2 INTERCONNECT SOLUTION:

   The 2012 reports from IRTS concludes that Cu and low- interconnects will probably represent the final conventional interconnect technology. And also concluded there are no metals with significantly lower resistivity than Cu. But it is eminent that Ag has significantly lower resistivity than Cu.

   The most Critical Challenges faced at nanometer scaling and their respective issues is given in Table No.2.

   Table No.2: Critical challenges and issues with interconnect design for future [6].

   MOST CRITICAL CHALLENGES AT NANOMETER SCALING	SUMMARY OF ISSUES
   Material Introduction of new materials to meet conductivity requirements	The rapid introductions of new materials/processes that are necessary to meet conductivity requirements create integration and material characterization challenges.
   Manufacturable Integration Engineering manufacturable interconnect structures, processes and new materials	Integration complexity, CMP damage, resists poisoning, dielectric constant degradation. Lack of interconnect/packaging architecture design optimization tool
   Reliability Achieving necessary reliability	New materials, structures, and processes create new chip reliability (electrical, thermal, and mechanical) exposure. Detecting, testing, modeling, and control of failure mechanisms will be key.
   Cost & Yield for Manufacturability Manufacturability and defect management that meet overall cost/performance requirements	As feature sizes shrink, interconnect processes must be compatible with device roadmaps and meet manufacturing targets at the specified wafer size. Plasma damage, contamination, thermal budgets, cleaning of high A/R features, defect tolerant processes, elimination/reduction of control wafers are key concerns. Where appropriate, global wiring and packaging concerns will be addressed in an integrated fashion.

2. Materials and Experimentals:

   1. Chemicals Used:

      1. Silver nitrate (AgNO3)

      2. Tannic acid (C76H52O46) and

      3. Carboxy Methyl Cellulose Sodium Salt (C8H16NaO8)

      4. Sodium carbonate (Na2CO3)

   2. Experimental procedure

      Silver nano-particles were synthesized by reducing its precursor silver nitrate solution. 0.17% of Sliver nitrate (AgNO3) solution dissolved in100ml of deionized water was mixed along with 0.1% of tannic acid dissolved 10ml of deionized water, similarly 0.1% of Carboxy Methyl Cellulose Sodium Salt dissolved in 10ml of deionized water, and 0.1% of Sodium carbonate dissolved in 10ml of de-ionized water. The mixture solution was stirred for one hour keeping it away from sunlight.

   3. Printing and Pattern:

      The prepared solution was used as an conductive ink and an interconnect pattern was drawn on the substrate using EPSON inkjet printer. The graphical structure of Interconnect patterns is shown below:

      Figure No.1: Proposed Structure of Silver Interconnect Patterns on Flexible Substrate

3. RESULTS AND DISCUSSIONS:

   1. SEM & XRD Analysis:

      The SEM images of prepared silver nano-particles is shown below:

      Figure No. 2: SEM image of Nano Silver

      Silver Nano ink prepared was filtered using a filter paper dried and then the dried samples were analyzed using XRD analysis. The results of XRD confirm the formation of silver nanoparticles (Ag).

      Figure No. 3: XRD plot of Nano Silver

      The particle size (D) of the prepared Nano Silver was calculated using Scherrers Formula and found to be in the range of 16nm to 28nm.

   2. Characterization of Nano Silver Interconnects:

   The VI characteristics of the interconnect lines are drawn with the help of NI Labview discrete components measurements.

   Figure No.4: VI characteristics of Nano Silver Interconnects

4. Conclusions:

The resistivity of the drawn Nano silver Interconnects, whose length is 1cm and width is 10µm, is found to be 0.0785µ.m at room temperature (30°C), which is proved to be much more conducting compared to an ordinary silver at 20°C. Hence, nano silver based interconnects can be used in IC chip replacing conventional Copper interconnects.

References:

1. Bamal, M. Performance Comparison of Interconnect Technology and Architecture Options for Deep Submicron Technology Nodes, Publication Year: 2006, Pg. 202 204.

2. Rakheja S. and Kumar V. Comparison of electrical, optical and plasmonic on-chip interconnects based on delay and energy considerations, 13th International Symposium on Quality Electronic Design (ISQED), 2012 , Page(s): 732 739.

3. Hong Li et. al., Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects, IEEE Transactions on Electron Devices, Volume: 56, Issue: 9, 2009, Pg. 1799 1821.

4. F. Anceau, A synchronous approach for clocking VLSI systems, Comput.-Aided Des., CAD-12: 11321146, 1993. IEEE J. Solid-State Circuits, SC-17: 5156, 1982. 26

5. M. A. Franklin and D. F. Wann, Asynchronous and clocked con- Communication in VLSI High-Speed Chips, Stanford, CA: Stantrolstructures for VLSI based interconnection networks, Proc. ford Univ., 1984, CRC Tech. Rep. 85-5.9th Annu. Symp. Comput. Archit., 1982, pp. 5059.

6. 2011 reports from ITRS.www.itrs.net/

AUTHORS PROFILE:

Cyril Robinson Azariah J. received his B.E. (Electronics and Communication Engineering) from the Anna University, Chennai in 2009 and M.Tech. (Nanotechnology) from Karunya University, in 2011. He is now Assistant Professor in Electronics and Communication Engineering Department, VSB Engineering College, Karur, Tamilnadu. His area of research interest includes Integration Challenges of Nanotechnologies with CMOS Microelectronics Platform and Nano Device Modeling.

Saravanan P. is now a postgraduate student in M.E. Applied Electronics from the department of Electronics and Communication Engineering, VSB Engineering College, Karur, Tamilnadu. His area of research interest includes Nanoelectronics and Advanced CMOS VLSI design.

Mohan Raj C. is now an undergraduate student from the department of Electronics and Communication Engineering, VSB Engineering College, Karur, Tamilnadu. His area of research interest includes CMOS VLSI Design and High Speed Networks.

Rahamathullah A. is now an undergraduate student from the department of Electronics and Communication Engineering, VSB Engineering College, Karur, Tamilnadu. His area of research interest includes VLSI Technology and Nanotechnology.

Veeramani T. is now an undergraduate student from the department of Electronics and Communication Engineering, VSB Engineering College, Karur, Tamilnadu. His area of research interest includes VLSI Design and Solid State Devices.

Vikram Singh R. is now an undergraduate student from the department of Electronics and Communication Engineering, VSB Engineering College, Karur, Tamilnadu. His area of research interest includes Advanced Nanoscale ULSI Interconnects.