A Comprehensive Review on Single-Phase Five-level Inverter Topologies

A Comprehensive Review on Single-Phase Five-level Inverter Topologies

V. Mahananda Reddy

PG student Electrical Engineering

VNIT-Nagpur Nagpur, India

K. Raghavendra Reddy

Research Scholor Electrical Engineering VNIT-Nagpur Nagpur, India

V. B. Borghate Associate Professor Electrical Engineering

VNIT-Nagpur Nagpur, India

Abstract Multilevel inverters have been developed to handle high power and high voltage in the flexible power systems. These inverters offer some inherent advantages over conventional 2-level inverters. High quality of the output voltage of the multilevel inverters is one of the most important advantages. Though the multilevel inverters hold attractive features, usage of more switches in the conventional configuration poses a limitation to its wide range application. The emphasis is on reducing the number of switches, which inturn reduces switching losses, and avoiding the capacitors, which may likely to cause voltage imbalance, and using less number of DC sources, which may increase additional isolation Transformer requirements, while designing a new prototype. A review has been done on the recently proposed topologies. A control strategy is proposed in this paper to minimize total harmonic distortion (THD) and a comparative analysis has been made with level shifted pulse width modulation (LSPWM).A prototype has been constructed with less switch count. The simulation analysis is

here requires minimum of Two Isolated DC Voltage sources or Series of Capacitors supplied from one DC source.

In this paper section II gives comparative analysis of various topological structures. The operating modes of adopted topology is discussed in section III. Section IV describes the proposed control scheme. The simulation and experimental results are presented in section V, followed by concluding remarks in section VI.

II. FIVE LEVEL INVERTER TOPOLOGIES

1. Type A topology

   In Type A there exist two sections namely Level selection part and Polarity Reversal part [1]. Level selection can be done by an Auxiliary bidirectional switch and a 4-switch Bridge takes care of polarity reversal enabling bipolar voltage levels. The basic five level Topology is shown in Fig. 1. (a)

   C 1

   S5

   done using PSIM-9.3 and validated through experimentation.

   Keywords Cascaded Multilevel Inverter, Hybrid Topologies, Total Harmonic Distortion, switch count.

   S1

   +

   D 3 D1

   +

   V – S5

   C1 + V

   LOAD

   –

   –

   S3

   S6

   +

   –

   S1 S3

   LOAD

   1. INTRODUCTION

   C2 D2 D 4 S4

   S2 C2 + S7 S2

   S4

   –

   V S8

   In order to reach high voltage and high power with available switching devices and improve output waveforms, multilevel inverters have been developed. Over the last decade, great advances

   (a) (b)

   +

   V V +

   have been made in multilevel inverter/converter topologies. In the literature, there are three traditional structures that were investigated in early and mid-1990s: the diode-clamped multilevel inverter, which derived from the neutral-point clamped inverter invented in 1979, the

   – S1

   +

   S6 S5

   S3

   –

   LOAD

   – S1

   V

   +

   +

   –

   S3

   –

   LOAD

   capacitor-clamped multilevel inverter or flying capacitor in 1992, and the cascade multilevel inverter in 1995. As multilevel inverters are

   + S4

   V

   –

   S2 D

   S5 S4 S2

   gaining increasing importance, newer topologies are being proposed to reduce part count for large number of levels in output voltage. These research breakthroughs have made the cascade multilevel

   (c) (d)

   +

   +

   S1 S2 S 3

   –

   –

   inverters a perfect topology for power system applications such as FACTS devices. Many papers have addressed the voltage unbalance problem that is inherent to all these multilevel inverters, unless each voltage level is provided by a separate and isolated dc source such as

   +

   S1 S2 S3 L

   +

   –

   – O

   D

   V V A

   V + V + –

   the cascaded multilevel inverter for medium voltage motor drives [8]. A generalized multilevel inverter topology was proposed to achieve

   S6 S5 S4

   S6 S5 S4

   LOAD

   automatic voltage balance of each dc voltage without additional balancing circuits in 2000.More recently published topologies[1-5] can categorized as Type-A, Type-B and Type-C Multi Level Inverter (MLI) topologies. Basic single phase five level topologies presented

   (e) (f)

   –

   Fig. 1. Recently proposed topologies

2. Type B topology:

   The Level selection in Type B contains switches only and/or Diodes and Polarity Reversal part [2,4]. The Level selection can be done by only four bidirectional switches and a 4-switch Bridge takes care of polarity reversal enabling bipolar voltage levels as depicted in Fig. 1.(c) and Fig. 1.(d)

3. Type C topology

   The Type C is formed by back-to-back connection of two H bridges [3-5], which has three leg structure with six unidirectional as depicted in Fig. 1.(e).In the literature same three leg topology is depicted in Fig.1.(f) as cross-connected structure and in Asymmetrical case this topology synthesizes seven levels with middle leg requiring bidirectional natured.

4. Cascaded H-Bridge multilevel inverter

   The cascaded H-bridge multilevel inverter single phase five level as shown in Fig.2. In conventional multilevel inverters cascaded H- bridge is best topology due to its inherent advantages for medium voltage and high power applications.

   50

   45

   40

   35

   30

   25

   20

   15

   10

   5

   CHB

   Fig. 1(a).

   Fig. 1(b).

   Fig. 1(c) & (e) & (f) Fig. 1(d)

   0

   5

   10

   15

   20

   25

   Output Voltage Levels

   0

   Number of Switches

   Fig. 3. Comparison of Various Topologies.

   In view of less number of switch count the type A suits. Type B Fig.1. (d) is preferable for a basic five level topology.

   1. OPERATING MODES OF IMPLEMENTED FIVE-LEVEL INVRTER

      The inverter produces output voltage in five levels: zero, Vdc,

      2Vdc, 0,-Vdc and -2Vdc.The advantages of the inverter topology are: Improved output voltage quality, smaller filter size, Lower

      Vdc

      S11

      S31

      A

      + VH1

      –

      Electromagnetic interferences, and Lower total harmonics distortion compared with conventional five level pulse width modulation

      ,Reduced number of switches compared to the conventional 5-level inverter. The cascaded H-bridges multilevel inverter introduces the

      Vdc

      S41 S12

      H1

      S12 S32

      VAN

      0

      0

      + VH2

      – N

      Vdc

      2Vdc

      -Vdc

      2 T

      – 2Vdc

      idea of using separate dc sources to produce an ac voltage waveform. Each H-bridge inverter is connected to its own DC source Vdc. By cascading the ac outputs of each H bridge inverter, ac voltage waveform is produced. By closing the appropriate switches, each H- bridge inverter can produce five different voltages: When a switch S1 and S3 of one particular H-bridge inverter are closed, the output voltage is 0 as shown in Fig.4. (a) .When a switch S1 and S2 are

      S42 S22

      H2

      Fig.2 Cascade H-Bridge inverter

5. comparision:

   Cascade H-Bridge s compared with various recent topologies. A comparative analysis has been done as listed in the Table I keeping in the view of minimizing number of switching devices for synthesizing five level output waveform. The analysis is further generalized for N levels as shown in Fig. 3. The topology shown in Fig. 1. (d) Is adopted for implementation for further analysis.

   Table. I. Comparison of various topologies

   closed, the output voltage is +Vdc as shown in Fig.4. (b). When a switch S1, S2 and S5 are closed, the output voltage is +2Vdc as shown in Fig.4. (c). When a switch S2 and S4 are closed, the output voltage is 0 as shown in Fig.4. (d).when a switch S3 and S4 of one particular H-bridge inverter are closed, the output voltage is -Vdc as shown in Fig.4. (e). When a switch S3, S4 and S5 are closed, the output voltage is -2Vdc as shown in Fig.4. (f). Where the H stands for one particular H-bridge inverter. Therefore, to obtain the total ac voltage produced by the multilevel inverter, these five distinct dc voltages are added together.

   S.no	S1	S2	S3	S4	S5	V0
   1.	On	On	Off	Off	On	2V
   2.	On	On	Off	Off	Off	V
   3.	On	Off	On	Off	Off	0
   4.	Off	On	Off	On	Off
   5.	Off	Off	On	On	Off	-V
   6.	Off	Off	On	On	On	-2V

   Table. II. Switching States.

   Sr.No	Topology	Number of Switches		Diodes
   		n levels	5 level
   1	Cascaded H-Bridge	2(n-1)	8	0
   2	Type A	(n+5)/2	5	4
   3	Type B Fig 1.b	n+3	8	16
   4	Type B Fig 1.c	n+1	6	0
   5	Type B Fig 1.d	(n+5)/2	5	1
   6	Type C	n+1	6	0

   +

   V – S1

   Is

   S

   V +

   1

   S3 –

   S3

   I0 + V0 –

   Is

   +

   V – S1

   S3

   I0 + V0 –

   Fundamental value of output voltage calculated using Fourier analysis

   VOut Bn * sin(nwt) ; n 0 to (3)

   LOAD

   S5

   S4 S2

   LOAD

   S5 Is

   S4 S2

   LOAD

   Is

   S4 S2

   B 2 1 (1)n n

   a(cos n1

   • cos n2

   ) b(cos n2

   )/ n

   V

   V

   V

   + + +

   – – –

   V f 1 4a(cos1 cos2 ) b(cos2 )/ (4)

   1. (b)

(c)

2 2

+

V – S1

S5

S4

V

+

–

S3

LOAD

S2

Is

+

V – S1

S5

V

+

–

S3

0 + –

I V0

LOAD

Is

S2

Is

+

V – S1

V

+

–

S3

0 + –

I V0

LOAD

Is

THD=100

S2

THD

VOrms V frms

V

2

frms

start

(5)

(d) (e)

Fig. 4. Operating modes

1. 0 Level (b) V Level (c) 2V Level

(d) 0 Level (e) -V Level (f) -2V Level

1. PROPOSED CONTROL SCHEME

   (f)

   No

   end

   1<900

   1 1+inc

   2 2

   Yes

   No

   thd<100

   Yes

   thd THD+inc

   In literature various switching procedure is like level-shifted sinusoidal pulse-width modulation (LS-SPWM), selective harmonic elimination (SHE) and SVPWM [10].The popular scheme is space- vector PWM but it becomes very complicated for more than three levels and hence the scheme is not dealt with in this paper. The

   No

   2<900

   No

   Thd<THD

   THD

   thd

   Yes

   proposed switching scheme to get minimum THD as shown in Fig.6.

   A. Calculation of switching angles

   THD Derivation For 5-Level:

   Yes

   2 2+inc

   Vo V2

   V1

   0 1

   -V1

   2

   -V2 2

   1

   Fig.6. Proposed control scheme.

   Using (2), (4), (5) equations and proposed control scheme shown

   2 T in fig.6. These implemented through Matlab programming switching angles1, 2 are calculated.

2. SIMULATIO RESULTS AND EXPERIMENTAL RESULTS

   10V +

   Fig. 5. Five level output voltage waveform.

   Rms value output voltage calculated below

   –

   0 +

   I V0 –

   load

   V 2 1 2 2

   2 2

   1 2

   Orms

   V1 d

   V1 d

   V1 d (1) +

   1

   2 2

   – 10V

   2V 2 V 2 2

   VO,rms

   1 2 1 2

   2 (2)

   Fig.7. Switched diode structure five-level inverter

   1. Simulation Results

      The switched diode structure is simulated using PSIM 9.3 for symmetrical sources of each Vdc=10V as shown in Fig. 7. The results are obtained with a resistive load with R=200 using LSSPWM with the switching frequency of 1.15 kHz with modulation index m=1.0. The voltage waveform and its FFT analysis as shown in Fig.8.

      The switched diode structure is simulated using PSIM 9.3 for symmetrical sources of each Vdc=10V as shown in Fig. 7. The results are obtained with a resistive load with R=200 using proposed control scheme with fundamental frequency. The voltage waveform and its FFT analysis as shown in Fig.9.

      Fig. 8. (a) Output voltage

      Fig. 9. (a) Output voltage waveform of proposed scheme

      VP1

      25

      20

      15

      10

      5

      0

      0 500 1000 1500 2000

      Frequency (Hz)

      Fig. 9. (b) FFT analysis

      Fig. 8. (b) FFT analysis

      Modulation index	%THD at fc= 1KHz	%THD at fc= 2 KHz	%THD at fc= 3 KHz	%THD at fc= 5 KHz
      0.3	106	106.27	106.1	108.7
      0.5	52.05	52.29	52.05	53.68
      0.7	41.3	42.07	41.83	42.25
      0.75	40.18	40.12	40.26	40.52
      0.8	38.28	38.37	38.38	38.70
      0.9	33.26	33.61	33.45	33.92
      1	26.81	27.04	26.78	27.30

      Table .III. Percentage of THD in Output voltage of recent topology

      TMS320F28335

      Gate Driver Using TLP-250

      DC supply

      Power ckt board

      LOAD

      From table we observed that as the modulation index increases percentage THD of output voltage decreases.

      Fig. 10. Hardware Setup

   2. Experimental results

      The prototype hardware setup as shown in Fig.10.the proposed algorithm implemented digitally by using DSP TMS320F28335 with the code composer studio 6.0. The Switched diode structure five- level inverter is accommodated in the laboratory shown in Fig. The IGBTs are used in the prototype are IRG4PH50UD and the diode used is RHRP30120. The recent multilevel inverter is tested with isolated dc power supplies of 10V, 2A with R-load R=200 ohm .The THD analysis is done using TPS2024B with application key, which can evaluate harmonics up to 50th order.

      The output voltage waveform and FFT analysis are shown in Fig.11 (a) and (b) with switching frequency 1.15 KHz and with proposed control algorithm in Fig.12 (a) and (b) respectively

      1. (b)

   Fig. 11. (a) Output voltage waveform (b) FFT analysis

   (a) (b)

   Fig. 12 (a) Output voltage waveform (b) FFT analysis

3. CONCLUSION

The comparison has been made on recent multi-level inverter topologies in view of reducing number of switches. A control strategy is proposed to reduce the THD in output voltage and the results are compared with those of LSPWM by simulation. The simulation results are validated by constructing the prototype. The results are summarized in the table IV. The proposed control scheme produce minimum THD with less switching loss. The topology implemented in this paper is an efficient one because it consists of less switches producing less switching loss, and it is operated by proposed control scheme which produces minimum THD with minimum switching loss.

TABLE IV Comparison of simulation and hardware results

REFERENCES

1. G. Ceglia, V. Grau, V. Guzmán, C. Sánchez, F. Ibáñez, J. Walter, A. Millán, M. I. Giménez, A New Multilevel Inverter Topology, Proceedings of the Fifth IEEE International Caracas Conference on Devices Circuits and Systems, Dominican Republic, vol. 1,pp. 212-218, May 2004.

2. Shalchi Alishah, R.; Nazarpour, D.; Hosseini, S.H.; Sabahi, M., "Switched-diode structure for multilevel converter with reduced number of power electronic devices," Power Electronics, IET , vol.7, no.3, pp.648,656, March 2014

3. Ebrahim Babaei,Mohammad Farhadi Kangarlu, Farshid Najaty Mazgar,Symmetric and asymmetric multilevel inverter topologies with reduced switching devices, Electric Power Systems Research 86. 2012,pp.122-130

4. Krishna Kumar Gupta, Shailendra Jain, Comprehensive review of a recently proposed multilevel inverter, IET Power Electron., 2014, Vol. 7, Iss. 3, pp. 467479 467 ,doi: 10.1049/iet-pel.2012.0438.

5. Ebrahim Babaei, Mohammad Farhadi Kangarlu, Farshid Najaty Mazgar,Symmetric and asymmetric multilevel inverter topologies with reduced switching devices, Electric Power Systems Research 86. 2012,pp.122-130

6. Javad Ebrahimi, Ebrahim Babaei,and Goverg B. Gharehpetian, A New Topology of Cascaded Multilevel Converters With Reduced Number of Components for High-Voltage Applications, IEEE Trans. Power Electronics, vol. 26, no.11, November 2011

7. Ebrahim Babaei, Mohammad Farhadi Kangarlu, Farshid Najaty Mazgar,Symmetric and asymmetric multilevel inverter topologies with reduced switching devices, Electric Power Systems Research 86. 2012,pp.122-130

8. Javad Ebrahimi, Ebrahim Babaei,and Goverg B. Gharehpetian, A New Topology of Cascaded Multilevel Converters With Reduced Number of Components for High-Voltage Applications, IEEE Trans. Power Electronics, vol. 26, no.11, November 2011

9. Electric Power Systems Research 86 (2012) 122 130 Electric Power Systems Research journal homepage Symmetric and asymmetric multilevel inverter topologies with reduced switching devices

10. Ahmed, I.; Borghate, V.B., "Simplified space vector modulation technique for seven-level cascaded H-bridge inverter," Power Electronics, IET , vol.7, no.3, pp.604,613, March 2014

V. Mahananda Reddy received B.Tech (Electrical) from JNTU Anantapur. He is presently

pursing M.Tech (Power Electronics & Drives) in Visvesvaraya National Institute of Technology (VNIT), Nagpur, India .His area of research interest in multilevel inverters and DC-DC converters.

K. Raghavendra Reddy received B.Tech (Electrical) from SCR Engg. College, under JNTU Hyderabad, M.Tech (Power Control & Drives) from National

Institute of Technology (NIT), and Rourkela, India .He worked at SIR C R REDDY College of engineering, Eluru.westgodavari.AP as Assistant Professor in the department of electrical Engineering. He is presently pursing his PhD from Visvesvaraya National Institute of Technology (VNIT),

Nagpur, India .His area of research includes multilevel converters, FACTS and Renewable energy sources

Vijay B. Borghate (M12) born in 1960, received B.E. (Electrical), M.Tech. (Integrated Power System) and Ph.D. from Visvesvaraya Regional College of

Engineering, under Nagpur University Nagpur, India in 1982, 1984 and 2007 respectively. He has worked as engineer during 1984-85 in

Maharashtra state electricity board, India, before joining the Visvesvaraya National Institute of Technology (VNIT), then VRCE, Nagpur, India as Lecturer in 1985. Presently, working as an Associate Professor in Electrical Department, in the same institute. His area of research includes resonant converters, multilevel converters.