A New Architecture Designed for Implementing Area Efficient Carry-Select Adder

A New Architecture Designed for Implementing Area Efficient Carry-Select Adder

D. Durgaprasad *1

Assistant Professor, Dept of ECE Vishnu Institute of Technology

A.P, India

A. M. V.Pathi *2

Assistant Professor, Dept of ECE Vishnu Institute of Technology

A.P, India

Ch. Rama Krishna *3

Associative Professor, Dept of ECE Vishnu Institute of Technology

A. P, India

C V Pradeep Kumar Reddy *4 Assistant Professor, Dept of ECE Vishnu Institute of Technology

A.P, India

Abstract: In this work, We have analyze the Conventional Carry Select Adder (CSLA) and Binary to Excess-1 converter (BEC) based CSLA contained logic operations and recognize the superfluous logic operations. The conventional CSLA contained superfluous logic operations are removed and introduce new logic operations for carry select adder. The carry select (CS) operation is performed before the calculation of final sum in newly introduced logic operations. We modify the design of carry select adder using newly introduced logic operations based logic units. From the synthesis results, the modified structure of CSLA yields significantly less area than the conventional CSLA and BEC-based CSLA. Due to the small carry-output delay, the modified CSLA design is best suitable for square-root (SQRT) CSLA.

Keywords: Adder, VLSI design, Arithmetic Unit.

I.INTRODUCTION

Low-power, area-efficient and high-speed VLSI systems are increasingly used in portable and mobile devices, biomedical instrumentation [2], [3] and multi standard wireless receivers. Addition is an obligatory operation that is crucial to processing the fundamental arithmetic operations. It is used extensively in many VLSI design hypothesis and is by far the most frequently used operation in a general purpose systems and in application specific processors, because the operations of subtraction, multiplication, division and address calculation usually relay on the operation of addition. Addition is often seen as an indispensable part of the arithmetic unit. It is dubbed the heart of any microprocessor, DSP architecture and data processing system.

A complex digital signal processing (DSP) system performance is basically improved using an efficient adder design. The ripple carry adder (RCA) design occupies small area, but carry propagation delay (CPD) is large for this adder. The carry propagation delay of the adders is reduced using Carry look-ahead and carry select (CS) methods.

The conventional carry select adder (CSLA) structure contains two ripple carry adders (RCA) that generates a pair of sum words and output carry bits corresponding to the anticipated input-carry ( Cin=0 and 1)

and selects one out of each pair of final-sum and final- output-carry [4]. A conventional CSLA has less CPD than an RCA, but the design is not attractive since it uses a dual RCA. Several designs are proposed to avoid dual use of RCA in CSLA design. Kim and Kim [5] introduce a new structure that contains one RCA and one add-one circuit instead of two RCAs, where the add-one circuit is implemented using a multiplexer (MUX). He et al.[6] proposed a square-root (SQRT)-CSLA for implementation of large bit-width adders with less delay. In a SQRT CSLA, CSLAs are connected in a cascading structure with increasing size. The main intention of SQRT-CSLA design is to provide a parallel path for carry propagation that helps to decrease the overall adder delay. Ramkumar and Kittur [7] introduce BEC-based CSLA. The BEC-based CSLA involves less logic resources than the conventional CSLA, but it has slightly higher delay. Common Boolean logic (CBL) based CSLA is also proposed in [8] and [9]. The CBL-based CSLA of [8] involves less logic resource than the conventional CSLA but it has higher CPD, which is equal to the RCA. To overcome this problem, a SQRT-CSLA based on CBL was proposed in [9]. The CBL-based SQRTCSLA design of [9] involves more logic resource and delay than the BEC-based SQRT-CSLA of [7]. We examine that the logic optimization largely depends on availability of redundant operations in the logic formulation, whereas adder delay largely depends on data dependence. In the existing designs, logic is optimized without considering the data dependence. In this work, We analyze the Conventional Carry Select Adder (CSLA) and Binary to Excess-1 converter (BEC) based CSLA contained logic operations and recognize the superfluous logic operations. The conventional CSLA contained superfluous logic operations are removed and introduce new logic operations for carry select adder. In this work, carry generator (CG) and CS units are optimized using newly introduced logic operations. We modify the design of carry select adder using optimized logic units. Due to optimized logic units, the new CSLA design involves significantly less area than the existing CSLAs.

1. LOGIC FORMULATION

   The Carry Select Adder (CSLA) has two units:

   For example the conventional CSLA perform addition operation on two n-bit operands. The RCA-1

   generates n-bit sum (s0) and output-carry (0 ) for input

   1. The sum and carry generator unit (SCG)

      carry cin

      = 0. The RCA-2 generates the n-bit sum (s1) and

   2. The sum and carry selection unit

      The most of the logic operations of the CSLA are present in SCG unit. Different structures have been proposed for SCG unit implementation. We analyze the conventional

      output carry (1 ) for input carry cin = 1. The logic expressions of the n-bit CSLA contained SCG unit are given as

      0() = () () 0 () = () ( 1(a)

      CSLA and BEC based CSLA contained SCG unit logic 0 0

      designs. The major aim of this analysis is to recognize the

      1() = 0() 0( 1) 1(b)

      superfluous logic operations and data dependence. In view of 0 0 1

      that, we eliminate all superfluous logic operations.

      0() = 0 () + 0() 0( 1) 0 = 0( 1) 1(c)

      1. Logic Operations Involved in Conventional CSLA

   1 0 0 1

   1

   The conventional structure of the CSLA [4] is

   1() = () () 1 () = () () 2(a)

   shown in Fig.1(a). The conventional CSLA structure 0 0

   contains two n-bit RCAs, where n is the adder bit-width. The

   1() = 1() 1( 1) 2(b)

   1 0 1

   n-bit RCA contained logic operations are performed in four

   stages that can be shown in Fig.1(b): They are

   1() = 1 () + 1() 1( 1) 1 = 1( 1) 2(c)

   1 0 0 1 1

   1. Half-sum generation (HSG)

      Where 0(1) = 0, 1(1) = 1, 0 1.

      1 1

   2. Half-carry generation (HCG)

      From the equations (1a)(1c) and (2a)(2c), the logic operations of {0(), 0()} is similar to that of

   3. Full-sum generation (FSG)

      0

      {1(), 1()}. The d

      0

      of the RCA-2 is optimized by

      0 0 esign

   4. Full-carry generation (FCG)

   removing redundant logic operations and constructs the RCA-2 by sharing the HSG &HCG of RCA-1. In [4], [5] the CSLA contains an add-one circuit instead of RCA-2. In [6] the CSLA contains BEC circuit in place of RCA-2. The Area-Delay-Power efficiency of the BEC based CSLA is better than the existing CSLAs, So the logic expressions of the BEC based CSLA contained SCG unit is discussed.

   B)Logic operations involved in BEC based CSLA

   The structure of the BEC based CSLA is shown in Fig. 2, It contains the n-bit RCA and BEC unit. The RCA

   calculates the n-bit sum 0 and output carry 0 for given

   1

   input carry in = 0. The sum 0 and carry 0 are given to

   1

   Fig.1.(a) Structure of the Conventional CSLA

   Fig.1.(b) The logic operations of the RCA is shown in split form

   the BEC unit and obtains (n + 1)-bit excess-1 code. The most significant bit (MSB) of the BEC represent the carry 1 and n-least significant bits (LSBs) of the BEC represent the sum

   1

   1

   1.

   Fig.2. Structure of the BEC-based CSLA

   The logic operations of the RCA of the BEC based CSLA structure are the same as those given in (1a)(1c). The logic operations of the CSLA contained BEC unit are given as

   1 1 1 1

   1 1 1 1

   1(0) = 0(0) 1 (0) = 0(0) 3(a)

   1() = 0() 1( 1)

   = ( 1) 4(f)

   (0) = 0(0) () = 0() ( 1) 4(g)

2. MODIFIED STRUCTURE OF THE CSLA

   The structure of the CSLA is modified based on the logic formulation given in equations (4a)(4g) and that can be shown in Fig. 3.

   1 1 1

   3(b)

   1() = 0 () 1( 1)

   1 1 1

   3(c)

   1 = 0( 1) 1( 1)

   1 1

   3(d)

   For 1jn-1

   1

   1

   We can observe from equations (1a)(1c) and equations (3a)(3d), the carry 1 of the BEC based CSLA

   depends on 0, but in conventional CSLA carry 1 is not

   1 1

   1

   1

   depends on 0. The data dependence in CSLA increases with the BEC method. We can perform the analysis on logic operations of the conventional CSLA and identify the superfluous logic operations. The logic units of the CSLA are optimized by removing the superfluous logic operations.

   We can observe from equations (1a)(1c) and (2a) (2c), in that logic expressions of 0 1 are equal except

   1 1

   the carry 0 and carry1, so that 0 = 1 = 0. We also

   1 1 0 0

   observe, the 0 and 1depend on {0,0, }, where 0 =

   0 = 1. The

   1 1

   riers and 1 are not depend on 0 and1,

   Fig.3.Modified Structure of the Carry Select Adder

   1

   1

   0 0 car 0 1 1 1

   1

   1

   1

   1

   so the logic operations of 0 and 1 can be performed before

   0 and 1. The select unit of the CSLA selects final sum

   It contains one half sum generator (HSG) unit, one full sum generator (FSG) unit, one carry generator (CG) unit

   1 1

   from the set (0, 1). We find that, in order to calculating the

   and one carry select (CS) unit. The CG unit contains two

   1 1

   {0,1} spent significant amount of logic resource and after

   carry generators (CG0 and CG1) for input-carry cin= 0 and

   1 1

   1

   1

   calculation the rejection of one sum word is not an efficient method. Instead, one can perform the calculation of the final sum by selecting carry word from the anticipated carry words0 1. The half-sum (0) is added with selected carry word to obtain the final-sum (s). This method has three design advantages: 1) The 0 calculation is not performed in the SCG unit 2) The n-bit select unit is needed in place of the (n + 1) bit select unit 3) The delay of the output-carry is minimum. All these features result in an areadelay and energy-efficient design for the CSLA. The redundant logic

   operations of equations (1a)(1c) and (2a)(2c) are eliminated and rearranged the logic operations of equations (1a)(1c) and (2a)(2c) based on their data dependence. The newly introduced logic operations for the CSLA is given as

   0() = () () 0 () = () () 4(a)

   cin= 1. Two n-bit operands are given to the HSG unit and that can produce n-bit half-sum word s0 and n-bit half-carry word c0.The outputs of the HSG unit are given to both CG0 and CG1.The CG0 generates the n-bit full-carry word 0 for input carry 0. The CG1 generates the n-bit full carry word

   1

   1

   1

   1

   1 for input-carry 1. The HSG unit gate level design is shown in Fig. 4. The optimization of the CG0 and CG1 logic circuits gives an advantage of the rigid input-carry bits. The optimized gate level designs of CG0 and CG1 are shown in Fig. 5 and Fig.6.

   0 0

   0() = 0( 1) 0() + 0() (0(0) = 0) 4(b)

   1 1 1

   1() = 1( 1) 0() + 0() (1(0) = 1) 4(c)

   1 1 1

   1

   1

   () = 0() ( = 0) 4(d)

   1

   1

   () = 1() () 4(e)

   Fig.4.Structure of HSG unit

   Fig.5.Structure of CG 0 for input-carry = 0

   Fig.6. Structure of CG 1 for input-carry = 1

   1

   1

   1

   1

   Depending on control signal cin, one final carry word is selected using CS unit from the two carry words available at its input. If cin=0, it selects 0 otherwise, it selects1. An n-bit 2-to-l MUX is used to implement the CS unit. However, we observe from the CS unit truth table, carry

   words 0 1 follow a specific bit pattern. If 0()= 1,

   Fig.8.Structure of the FSG unit

3. SQURE ROOT (SQRT) CSLA DESIGN

   The multipath carry propagation feature of the CSLA is fully oppressed in the SQRT-CSLA [6], which is collected of a chain of CSLAs. CSLAs with increasing size are used in the SQRT-CSLA design to remove the most consensus in the carry propagation path. The large-size adders are realized using SQRT CSLA with less delay than the same size single-stage CSLA. However, the carry propagation delay between the CSLA stages of SQRT-CSLA is crucial for the overall adder delay. The modified CSLA design is more favourable for area delay efficient implementation of SQRT CSLA than the existing CSLA designs, since the output carry is generated premature with multipath carry propagation feature .A 16-bit SQRT-CSLA design with modified CSLA structure is shown in Fig. 9, The

   16-bit SQRT CSLA uses the 2-bit RCA, 2-bit CSLA, 3-bit CSLA, 4-bit CSLA and 5-bit CSLA. To exhibit the

   1 1 1

   1

   1

   then 1()= 1, irrespective of0() 0(), for 0 j n

   1. The CS unit logic optimization uses this feature. The

   optimized gate level design of the CS unit is shown in Fig. 7, which is composed of n ANDOR gates. The CS unit generates the final carry word c. The output carry cout is the MSB of c and (n 1) LSBs of c are XORed with (n 1) MSBs of half-sum (s0) in the FSG and obtains (n 1) MSBs of final-sum(s). The LSB of half sum (s0) is XORed with cin to acquire the LSB of s. The structure of the Final Sum Generator (FSG) is shown in Fig.8.

   Fig.7.Structure of the CS unit

   advantage of the modified CSLA design in SQRT-CSLA, we calculate the area and delay of the modified CSLA design based SQRT CSLA and the conventional CSLA design based SQRT CSLA for bit-widths 16. The modified CSLA design based SQRT-CSLA design has less area than the existing SQRT CSLA.

   Fig.9.Structure of the SQRT CSLA

4. RESULTS AND PERFORMANCE ANALYSIS

   We have verified the modified structure and existing structures of carry select adder by writing VHDL code, Simulated and Synthesized.

   The simulation result of the carry select adder (CSLA) is shown in Fig.10.

   Fig.10.Simulation Result of the CSLA

   Table I and Fig.11 shows the comparison between the modified CSLA design, Conventional CSLA design and BEC based CSLA design in terms of Delay, Number of LUTs and Number of Slices.

   TABLE I:Comparison between CSLA Designs

   Design	Delay (ns)	No. of LUTs	No. of Slices
   Conventional CSLA	10.382	27	15
   BEC Based CSLA	13.767	27	15
   Modified CSLA	12.738	25	14

   Fig.11.Comparision Graph of CSLA structures

   We have also verified the modified CSLA based 16- bit SQRT CSLA design and conventional CSLA based 16- bit SQRT CSLA by writing VHDL code, Simulated and ynthesized.

   The simulation result of the SQRT CSLA is shown in Fig.12.

   Fig.12.Simulation Result of the SQRT CSLA

   Table II and Fig.13 shows the comparison between the modified CSLA based 16-bit SQRT CSLA design, Conventional CSLA based 16-bit SQRT CSLA design in terms of Delay, Number of LUTs and Number of Slices.

   TABLE II: Comparison between SQRT CSLA Designs

   Design	Delay (ns)	No. of LUTs	No. of Slices
   Conventional CSLA Based SQRT CSLA	15.434	37	22
   Modified CSLA Based SQRT CSLA	16.33	34	21

   Fig.13.Comparision Graph of SQRT CSLA structures

5. CONCLUSION

Ch. Rama Krishna was born in A.P, India. And he completed his M.Tech in JNTUK in 2008. and he has totally 11 years experience. Presently he is working as Associate professor in VIT, Bimavaram. His area of research is Antenna and wave propagation.

Ch. Rama Krishna was born in A.P, India. And he completed his M.Tech in JNTUK in 2008. and he has totally 11 years experience. Presently he is working as Associate professor in VIT, Bimavaram. His area of research is Antenna and wave propagation.

C V Pradeep Kumar Reddy, was born in A.P, India, Completed M.Tech in EMBEDDED SYSTEMS at SRM University, Chennai in the year of 2012 and B.E from P B College of Engineering in the year of 2007 in Electronics& Communication Engineering. He worked as an Assistant Professor in WISE and presently working as an Assistant Professor in Vishnu Institute of Technology, Bhimavaram, A.P, India. His research interests in VLSI Design and Embedded Systems.

C V Pradeep Kumar Reddy, was born in A.P, India, Completed M.Tech in EMBEDDED SYSTEMS at SRM University, Chennai in the year of 2012 and B.E from P B College of Engineering in the year of 2007 in Electronics& Communication Engineering. He worked as an Assistant Professor in WISE and presently working as an Assistant Professor in Vishnu Institute of Technology, Bhimavaram, A.P, India. His research interests in VLSI Design and Embedded Systems.

We analyzed the Conventional Carry Select Adder (CSLA) and Binary to Excess-1 converter (BEC) based CSLA contained logic operations and recognize the superfluous logic operations. The conventional CSLA contained superfluous logic operations are removed and introduce new logic operations for carry select adder. The carry select (CS) operation is performed before the calculation of final sum in newly introduced logic operations. We modify the design of carry select adder using newly introduced logic operations based logic units From the synthesis results, the modified structure of CSLA yields significantly less area than the conventional CSLA and BEC- based CSLA. Due to the small carry-output delay, the modified CSLA design is most suitable for square-root (SQRT) CSLA. The modified CSLA based SQRT CSLA design yields less area than the existing SQRT CSLA designs.

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D. Durga Prasad was born in A.P, India, Completed M.Tech in VLSI System Design (VLSISD) at Swarnandhra college of Engineering, Seetharampuram in the year of 2015 and B.Tech from Vishnu Institute of Technology in the year of 2013 in Electronics &Communication engineering. Presently working as an Assistant Professor in Vishnu Institute of Technology, Bhimavaram ,A.P, India. His research interests in VLSI Design and Communication Systems.

D. Durga Prasad was born in A.P, India, Completed M.Tech in VLSI System Design (VLSISD) at Swarnandhra college of Engineering, Seetharampuram in the year of 2015 and B.Tech from Vishnu Institute of Technology in the year of 2013 in Electronics &Communication engineering. Presently working as an Assistant Professor in Vishnu Institute of Technology, Bhimavaram ,A.P, India. His research interests in VLSI Design and Communication Systems.

A. M. V .Pathi born in A. P., India. Completed M. Tech. & B. Tech. from Swarnandhra College of Engineering and Technology, Seetharampuram. Presently working as Asst. Prof in Vishnu Institute of Technology, Bhimavaram. His Research work interests in VLSI design

A. M. V .Pathi born in A. P., India. Completed M. Tech. & B. Tech. from Swarnandhra College of Engineering and Technology, Seetharampuram. Presently working as Asst. Prof in Vishnu Institute of Technology, Bhimavaram. His Research work interests in VLSI design