A New Three-Phase Interleaved Isolated Boost Converter with Solar Cell Application

DOI : 10.17577/IJERTV2IS70275

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A New Three-Phase Interleaved Isolated Boost Converter with Solar Cell Application

K. Srinadh

Abstract In this paper, a new three-phase high power dc/dc converter with an active clamp is proposed. The converter is capable of increased power transfer due to its three-phase power configuration, and it reduces the rms current per phase, thus reducing conduction losses. Further, interleaved operation of three- phase boost converter reduces overall ripple current, which is imposed into fuel cells and realizes smaller sized filter components, increasing effective operating frequency and leading to higher power density. Each output current of three-phase boost converter is combined by the three-phase transformer and flows in the continuous conduction mode by the proposed three-phase PWM strategy. An efficiency of above 96% is mainly achieved by reducing conduction losses and switching losses are reduced by the action of active clamp branches, as well. The proposed converter and three-phase PWM strategy are analyzed, simulated and implemented in hardware. Experimental results are obtained on a 500W prototype unit, with all of the design verified and analyzed.

Keywords three-phase dc/dc converter, isolated boost converter, interleaved operation, continuous conduction mode, three-phase PWM strategy

  1. INTRODUCTION

    Fuel cells are identified as a future energy source due to their efficient and clean energy characteristics; furthermore, they produce low varying dc voltage in the range of 26 ~ 42 V for residential power application. Power conditioning system in the residential use usually consists of a low-voltage fuel cell as the primary source, a dc/dc converter to obtain isolated high voltage, and a dc/ac inverter to connect commercial ac voltage [1]. Since a dc/ac inverter supplies power into a 220V ac utility, an isolated dc/dc converter has to convert low varying dc voltage to high constant dc voltage at around 370 V. Therefore, a high power dc/dc converter with a high voltage ratio is needed, and a transformer is usually employed for boosting voltage as well as for isolation. Research has been focused on the three-phase dc/dc converter due to the benefits it can offer, such as high power density and high quality waveforms. However, most of the work thus far has been done on topology and PWM strategy for a voltage-fed dc/dc converter [2]-[5]. In recent, a three-phase current-fed dc/dc converter has been studied but it operates in the discontinuous conduction mode in spite of several advantages [6].

    In this paper, development of a three-phase interleaved isolated boost converter with active clamp is proposed. Major features of the proposed converter include: (1) an increased power rating through employing a three-phase power transfer into dc/dc conversion, (2) a reduction of the ripple currents into the solar cells by an interleaved operation, (3) a reduction in conduction losses by continuous current conduction in the switches, transformer windings and input inductors, (4) an alleviated voltage surges and switching noises by three-phase active clamp branch, and (5) a lowering of the transformer turns- ratio by using voltage boost property inherited by boost topology. Due to these advantages, this converter is highly suitable for the interface between a low-voltage high-power solar cell source and an inverter load. It may also be extended to other low-voltage sources, such as batteries and photovoltaic which need high-voltage high-power dc/dc conversion capability.

  2. PROPOSED 3-PHASE DC/DC CONVERTER

    Fig. 1 shows the proposed three-phase interleaved isolated boost converter with active clamp. It consists of a three-phase dc/dc converter, whose outputs are connected to a three-phase full-bridge diode rectifier through a delta-delta wound three- phase transformer. The three-phase dc/dc converter is divided into a three-phase boost converter configured as three main

    MOSFET switches (S1 ~ S3) for three-phase boost converter, three auxiliary MOSFET clamp switches (SC1 ~ SC3) and common clamp capacitor CC for three-phase active clamp

    branch, and three dc boost inductors (L1 ~ L3) acting as a current source for each phase. Interleaved PWM operation occurs

    through the three dc boost inductors L1 ~ L3 of the three-phase boost converter and increases effective switching frequency of

    output current Ii of solar cells. Thus, it reduces overall ripple current, which is imposed into soalr cells and realizes smaller sized filter components. The active clamp branch reduces switching losses by zero voltage switching (ZVS) through the use of resonance between leakage inductances of the three-phase transformer and entire capacitances of clamp capacitance, output capacitances of MOSFET switches, and stray capacitances of the transformer. Furthermore, it clamps voltage across the switches and thus, no ancillary snubber is required in either the primary or secondary sides. The employed three-phase power structure increases input current and output voltage chopping frequencies by a factor of three and thus, reduces size of reactive filter

    Figure 1. Power circuit configuration of three-phase isolated boost converter with active clamp

    Figure 2. Simplified converter configuration

    components; lowers rms current through the main switches and transformer windings by distributing currents into three-phase paths; increase power transfer capability with the same current rate and voltage rate of switch. In addition, continuous current

    conduction in three-phase converter output current Ia ~ Ic and input current Ii leads to a highly efficient operation.

    Due to these characteristics, the proposed converter is highly

    recommended as the interface between a low-voltage high- power solar cell source and a cascaded inverter stage. It is also suitable for other low-voltage sources, such as batteries and photovoltaic, which supply high-voltage, high-power dc to the next power stages.

  3. PROPOPSED PWM STRATEGY

    Fig. 2 shows a simplified circuit of the proposed three- phase isolated boost converter introduced in Fig. 1 and clamp capacitor CC and output capacitor CO are replaced by voltage

    sources VC and VO, respectively. The boost inductors L1 ~ L3 are also replaced by current sources IL1 ~ IL3 respectively, during each switching period. Fig. 2 includes delta-delta

    connected three-phase transformer configuration, where iap represents the primary winding current in phase A and ia is output current of boost converter in phase A.

    Fig. 3 shows the ideal current waveforms of phase currents ia ~ ic and transformer primary currents iap ~ icp; the gating signals vG1 ~ vG3 for main switches S1 ~ S3, resulted phase voltages va ~ vb and line-to-line voltages vab ~ vca.

    The operation procedure for the proposed converter is divided into 8 modes. Fig. 4 shows a set of eight topological states in phase A which occur during one switching interval

    TS and analysis is focused on iap, the

    Figure 3. Ideal waveforms of the proposed converters

    primary current of the transformer in phase A. The current paths of input boost inductors which are regarded as constant current sources are not marked to avoid complexity.

    Before t0 (Fig. 4 (h)) : The phase A main switch S1 and phase B main switch S2 are turned on. Thus, the boost inductor L1 and L2 charge energy from solar cells Vi. The transformer primary current of phase A, iap have been freewheeling through D4 and D6 because the line-to-line

    voltages of the phase, vab and vabs are zero. The current iap have been flowing to the negative directin and has a

    the leakage inductance Llk, finite time interval (T1) is required and such a transition is called the current

    commutation time, which is t0 ~ t1. Equation (1) and (2) show the voltage magnitude of clamp voltage VCc and the current commutation time T1 respectively. The transformer primary current, iap through the leakage inductance Llka increases as a slope determined by the clamp voltage VCc as shown in (3). Equation (5) evaluates the current iap at t1.

    V Vi (1)

    1

    constant value. The current of phase C, icp have been increasing.

    t0 ~ t1 (Fig. 4 (a)) : At t0, the phase A main switch S1 turns off. The transformer primary line-to-line voltage vab reaches the positive value of clamp capacitor voltage VCc and vca becomes zero. On the other hand, the transformer secondary voltages vabs and vcas are

    being sustained at zero and +Vo respectively. Thus, voltages across the leakage

    inductors Llka and Llkc are +VCc and -VO (reflected output

    voltage to the transformer primary) respectively. Due to

    Cc

    VO '

    i

    ap

    D

    V

    O

    n (2)

    V

    Cc t iap (t0 ) (3)

    L

    lk

    1. Interval 1 (t0 ~ t1) (b) Interval 2 (t1 ~ t4)

    (c) Interval 3 (t4 ~ t5) (d) Interval 4 (t5 ~ t6)

    (e) Interval 5 (t6 ~ t7) (f) Interval 6 (t7 ~ t10)

    '

    '

    (g) Interval 7 (t10 ~ t11) (h) Interval 8 (t11 ~ t0 ) Figure 4. Eight topological states in phase A

    t1 t0

    V V ' T

    Cc O S

    V T1

    Cc 3

    clamp voltage -VCc as shown in (11). The interval of this

    (4) period is equal to T1 which is the commutation time.

    V

    Cc

    iap (t1 ) T1 iap (t0 )

    L

    (5)

    V

    i Cc

    ap

    L

    t iap (t1 ) (11)

    lk

    where n = N2/N1 (turn-ratio of the transformer), TS

    (period), D (duty ratio), Llk = Llka = Llkb = Llkc.

    lk

    t7 t6 T1 (12)

    t1 ~ t4

    D tur

    (Fig. 4 (b)) : When the current iap exceeds icp at t1, off and D turns on resp vely. Th

    t7 ~ t10 (Fig. 4 (f)) : When the current iap falls below the

    icp at t7, D1 turns off and D4 turns on respectively. Thus, the

    4 ns 1

    ecti

    us, the

    transformer secondary voltage vabs is changed to -VO. The

    transformer secondary voltage vabs is changed from zero to

    +VO and the current iap through the leakage inductance Llka

    increases. The slope is determined by the voltage difference

    between the clamp voltage +VCc and the reflected output

    current iap through the leakage inductance Llka decreases as a slope determined by voltage difference between the negative

    clamp voltage -VCc and the reflected negative output voltage

    -V as shown in (13). The interval of this period is same as

    voltage +V . Equation (7) shows the interval of current O

    O

    period. Equation (8) evaluates the current iap at t4.

    V V '

    (7).

    i

    i

    V V '

    Cc O

    i

    ap Cc

    L

    lk

    O t iap (t1 ) (6)

    ap

    L t iap (t0 )

    lk

    (13)

    V V ' T

    T Cc O S

    S

    S

    t4 t1 t10 t7 T1 . (7)

    iap (t10 )

    L

    T1 iap (t0 ) (14)

    3

    V V ' T

    OST1iap

    lk 3

    t10 ~ t11 (Fig. 4 (g)) : At t10, the phase B main switch S2 turns on. The primary line-to-line voltage vab becomes

    iap (t4 ) Cc

    L

    lk 3

    (t1) (8)

    zero and vbc reaches the negative value of clamp capacitor voltage, -VCc. Thus, the transformer primary current iap increases and ibp decreases respectively. The transformer

    t4 ~ t5 (Fig. 4 (c)) : At t4, the phase B main switch S2 turns off.

    The primary line-to-line voltage vab becomes zero and vbc reaches the clamp capacitor voltage +VCc. Thus, the transformer primary current iap decreases and ibp increases. The transformer primary

    current iap through the leakage inductance Llka decreases as a slope determined by -VO as shown in (9). The interval of this period and

    primary current iap through the leakage inductance Llka

    O

    O

    increases as a slope determined by +V as shown in (15) and

    ibp through the leakage inductance Llkb decreases as a slope determined by -VCc as shown in (16). The interval of this period and iap(t11) are same as (4) and iap(t0) respectively.

    the value of iap(t5) are same as (4) and (5) respectively.

    V '

    V '

    i

    i

    O

    ap L

    t iap (t10 )

    (15)

    i O lk

    ap L

    t iap (t4 )

    (9) V V

    lk

    t5 ~ t6 (Fig. 4 (d)) : When the current ibp exceeds iap at

    t5, D6 turns off and D3 turns on respectively. Thus, the

    ibp

    Cc

    L

    lk

    t ibp (t10 )

    Cc

    L

    lk

    t iap (t1 ) (16)

    transformer secondary voltage vabs is changed to zero. Since the primary line-to-line voltage vab keeps remaining to zero, the transformer primary current iap freewheels

    through D1 and D3. The interval of this period is as shown in (10).

    2

    t t D T T (10)

    t11 ~ t0 (Fig. 4 (h)) : The modes from interval 1 to 8 in Fig. 4 is repeated periodically and continuously.

    The voltage transfer ratio (VTR) equation of the proposed converter can be derived by integrating the iSc1 curve with respect to time from t0 to t0 as follows.

    6 5 3 S 1

    V n B B2 4

    O

    O

    (17)

    t6 ~ t7 (Fig. 4 (e)) : At t6, the phase A main switch S1 turns on. The primary line-to-line voltage vab reaches the negative value of VCc and vca becomes zero. Thus, the transformer primary current iap decreases until it reaches the level of iap(t0). The

    current iap through the leakage inductance Llka decreases as a slope determined by the

    Vi (1 D) 2

    where, B 75Llk

    RLTS

    Normalized voltage transfer ratio (NVTR) is defined such as (18). It removes an effect of transformer turns- ratio in the overall gain and represents a gain by converter topology.

    O

    O

    ~ V

    V

    nVi

    (18)

    FIG 8: INPUT CURRENT

  4. SIMULATION AND EXPERIMENTAL RESULTS

    1. Simulation

      Fig. 5 shows simulation waveforms for output power PO = 500 W, Vi = 30 V and VO = 370 V, and the waveforms are obtained for a 25 kHz switching frequency (TS = 40 sec), 330 H boost inductor L1 ~ L3, 13 H leakage inductance Llks and a three-phase transformer which has a 2 mH magnetizing inductance Lm and 1 : 5 turn-ratio (n = 5). Fig. 5

      (a) shows the transformer primary current iap and the currents

      ibp , icp in phases B, C are identical except for a 120o phase displacement. It should be noted that the transformer primary currents flow continuously. Fig. 5 (b) shows the clamp current

      iSc1.

      FIGURE 6:PULSES GENERATION

      FIG7 : INPUT VOLTAGE

      IG9: VOLTAGE IN SECONDARY WINDING OF TRANSFORMER

      FIG 10 : CURRENT ACROSS THE INDUCTOR

      FIG 11:O/P VOLTAGE

    2. Experimental Results

    To verify the proposed converter and PWM strategy, a 500 W prototype unit has been built and tested. It consists of a digital signal processor (DSP: TMS320LF2407) and a field- programmable gate array (FPGA: EPM7128) board to generate PWM patterns for the isolated boost converter; a gate driver board; three legs of main switch branch with active clamp each other; a delta-delta wound three-phase transformer; and three- phase full-bridge rectifiers.

    The proposed converter prototype is experimented under 30 V of input voltage and 370 V of output voltage, 500 W load conditions and the same parameters in the simulation are used.

    Fig. 6 shows the waveforms of transformer primary currents iap, ibp and icp at duty D = 0.6, where three-phase current waveforms

    have 120o phase displacement each other and flow in the

    ontinuous conduction mode. Fig. 7 shows transformer primary

    current waveforms in phase A, iap and clamp current iSc1 waveforms, and The waveforms are well matched to the simulation result in Fig. 5. The waveforms in Fig. 8 show

    interleaved input current ii and three-phase input boost inductor currents iL1, ~ iL3 flowing through boost inductor, L1 ~ L3,

    respectively. The interleaved input current ii shows typical interleaved operation results; three-times increased switching

    frequency and reduced ripple magnitude. Fig. 9 shows normalized voltage transfer ratio (NVTR) of the proposed converter, where solid line represents calculated data by (17) and x marks represent experimented data. The curve in Fig. 10 shows the measured efficiency under loads ranging from 100W to 500W. The efficiency above 96 % is achieved and it is caused by continuous current conduction through transformer and interleaved operation in the three-phase boost converter. Switching losses are reduced by the action of active clamp branches, as well.

  5. CONCULSION

A new three-phase dc/dc converter and three-phase PWM strategy have been proposed in this paper. In the proposed converter, interleaved operation of three-phase boost converter reduces overall ripple current, which is imposed into solar cells and thus. The interleaved operation increases effective operating frequency and thus, leads to realization of smaller sized filter components. In addition, the proposed three-phase PWM strategy transfers energy in the continuous conduction mode and three-phase paths. Further, three-phase clamp branch mitigates not only switching losses by zero voltage switching but also electromagnetic noises caused by hard-switched voltage

spikes. These characteristics of the proposed converter reduce operating losses significantly and result in the whole converter efficiency above 96%. Inherent voltage boost characteristics of the boost converter increase the voltage

transfer ratio in addition to the transformer turns ratio. These advantages make this converter suitable for low dc voltage renewable energy sources such as ultra capacitors.

REFERENCES

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  2. A.R. Prasad, P.D. Ziogas, and S. Manias, Analysis and design of a three-phase off line DC-DC converter with high-frequency isolation, IEEE Transactions on Industry Applications, vol. 28, pp. 824 – 832, July-Aug. 1992

  3. D. de Souza Oliveira and I. Barbi, A three-phase ZVS PWM DC/DC converter with asymmetrical duty cycle for high power applications, IEEE Transactions on Power Electronics, vol. 20,

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  4. J. Jacobs, A. Averberg, and R. De Doncker, A novel three-phase dc/dc converter for high-power application, in Power Electronics Specialists Conference, 2004, pp. 1861 1867

  5. C. Liu, A. Johnson, and J. Lai, A novel three-phase high-power soft-switched DC/DC converter for low-voltage solar cell applications, IEEE Transactions on Industry Applications, vol. 41, pp. 1691 – 1697, Nov.-Dec. 2005

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