A New Topology for Asymmetrical Multilevel Inverter

A New Topology for Asymmetrical Multilevel Inverter

A Cascaded Multilevl Inverter with Reduced Number of Switches

Miss. Somya Shrivastava

Department of Power Electronics

M.I.T Mandsaur Mandsaur, India

Mr. C. Veeresh

Department of Electrical and Electronics MIT Mandsaur

Mandsaur, India

Abstract The main objective of this paper is to design of new asymmetrical multilevel inverter topologies with reduced number of switches. This will give an efficient way of producing multistep waveform with reduced harmonics.

Keywords Multilevel Inverter; Topologies;Harmonics;Power System; Efficiency

distortions. With more voltage levels in the inverter the waveform it creates becomes smoother.

III. PREPARE YOUR PAPER BEFORE STYLING

1. INTRODUCTION

   Today demand of electrical power is increasing to a great extent. So to meet the requirements, generation of power is also increases. This can be achieved by storing the power through batteries in the form of D.C and this stored energy can be utilized by converting into A.C power with the help of INVERTER. The multilevel inverter have become more popular over the years in electric high power applications with the promise of less disturbances, possibility to function at lower number of switches and switching frequencies. In addition the advantage of multi level inverter is, it can also be use renewable energy resources.

   In multilevel inverter, output level occurred in a proper way so as to achieve the approximated sinusoidal wave. If these levels are more, then their stair case waveform is closed to sinusoidal waveform. For getting more levels various topologies are proposed, but the number of levels achieved is limited to circuit complexity as well as cost of equipment. That is why this paper is focused on making circuit simple as much as possible with less number of switching devices.

   In this paper a new multilevel inverter topology is introduced and analyzed. This is a cascaded asymmetrical multilevel inverter with reduced number of switches.

2. BASIC COCEPT OF MULTILEVEL INVERTER

   Conventional two level inverter is mostly used today to

   Fig. 1. Basic two level inverter

   Fig.2. PWM modulation

   III . PROPOSED TOPOLOGY FOR MULTILEVEL INVERTER

   The main objective of this proposed topology is to design the multi level inverter with reduced number of switches and voltage sources. The output voltage can be obtained with less distortion and losses and as smooth as possible in the form of pure sinusoidal waveform.

   The following figure gives the representation of proposed topology as a basic cell configuration.

   E

   E1

   G S1

   E2

   D1

   C +

   generate an A.C voltage from D.C voltage. The two level inverter can only create two different output voltages for the

   IGBT unidirectional switch

   S2 D2

   V0 OUTPUT

   –

   load, Vdc/2 or Vdc/2 (when inverter is fed with Vdc) as shown in figure1. To build up an AC output voltage these two voltages are usually switched with PWM as shown in figure 2.

   The concepts of multilevel inverter do not depend on just two levels of voltage to create on AC signal. Instead several voltage levels are added to each other to create a smoother stepped waveform with lower dv/dt and lower harmonic

   E1 E2

   Fig.3. basic unit cell for proposed topology

   This basic cell consists of Two unidirectional IGBT switches and two diodes and two DC sources E1 and E2 (E2>E1). Proposed basic cell can produce two output voltage levels across the load connected. When the switch S1 is turned ON

   then the output voltage across the load is E1 Volts. Then if switch S2 is triggered by the gate signal the output voltage V0 across the load is E2 Volts by keeping the other switch is in OFF mode.

   switching ON by S2, S3 and turn OFF of S1, S4 in H-bridge with combination switching sequence of positive voltage values as shown in table 3.

   STATE	S1	S2	OUTPUT (V0)
   1	ON	OFF	E1
   2	OFF	ON	E2

   Output voltage V0

   E1 0

   Table1. Switching sequence f the cell

   E1

   E1

   E2

   S2 ON

   Time, t

   Table 3: switching sequence for basic 5-Level MLI

   V0	Ste p	S1	S2	D1	D2	T1	T2	T3	T4
   0	1	0	0	0	0	1	1	0	0
   						0	0	1	1
   E1	2	1	0	1	0	1	0	0	1
   2E1	3	0	1	0	0
   -E1	4	1	0	1	0	0	1	1	0
   -2E1	5	0	1	0	0

   The table 3 represents the five different values of output waveform with values 0, E1, 2E1, -E1, -2E1 and 1 represents ON state and 0 represents OFF state. The peak voltage across the load is 2E1.

   V. THE GENERALIZED FORMAT OF MLI

   The general circuit for obtaining different levels of output waveform with reduced number of switches can be possible

   S1 S1

   ON ON

   Fig.4. output voltage waveform of cell

   1. PROPOSED TOPOLOGY FOR 5- LEVEL

      The basic proposed asymmetric multilevel inverter (AMLI) for generating five level AC stepped voltage waveform across the load is as shown in the figure. In the circuit, the

      through this topology. Hence analysis of this topology can be done.

      1. General circuit diagram for definite no. of levels

         The following fig.6 represents the cascaded connection of basic cell topologies so as to produce the definite no. of levels.

         E

         requirements of switches and voltage sources as: two voltage sources of E1, E2= 2E1, two switches of unidirectional type S1,S2, a H-Bridge consists of 4 unidirectional switches such

         G

         C

         IGBT

         +

         S1n

         Vn

         D1n D2n

         S2n

         as T1,T2,T3,T4 and two diodes as D1,D2. Here unidirectional switch can be IGBT (Insulated Gate Bipolar Transistor) with anti-parallel diode mainly used for medium

         unidirectional

         switch

         E1n E2n

         Generalized

         CELL n

         –

         + S1 S2

         power applications. Two possible voltage levels can be generated as E1and 2E1 by switches S1 and S2 turned on with respectively as well as negative levels are also possible by use of H- Bridge, such as (E1) , – (2E1).

         S12

         D12 E12

         to n cells

         S22

         E22

         D22 CELL –

         S3 S4

         H-Bridge

         + V0

         V2

         2

         –

         S1 T1 T2

         LOA

         + –

         D1

         D2

         S2

         T3 T4

         S11

         D11

         E11

         S21

         E21

         +

         V1

         D21

         CELL 1

         E1 E2= 2E1

         –

         Fig.5. asymmetrical multilevel inverter for 5-Level output

         For production of 5-level output for basic proposed topology, proper switching sequence is required as in TABLE 3. For level E1, switches S1,D1,T1,T4 are turned ON and at this instant the diode D2 is in reverse bias as E1 voltage makes the this diode reverse bias. For level E2=2E1, switches used are S2, T1, T4. At this instant also diode D2 is also reverse bias. For negative voltage values in the output, just by

         Fig.6. generalized format of developed cascaded multilevel inverter topology

         In this extended proposed topology, n no. of basic cells is connected in series to produce multilevel output V0. This output is sum of individual cell output voltages. The following is the expression form,

         V0 = i =1, 2n Vi

         In the above equation V1, V2,Vn are individual output voltages across cell1, cell2,..cell n. proper switching ON and OFF of the switches required output can be obtained.

      2. Algorithm used for voltage calculation

      Third proposed method for calculating the values of voltage sources is as shown in the below. In this method asymmetry of voltage sources is more. It is important to note that if asymmetry increases the complexity and cost of inverter equipment is also increases, but the steps in output waveform are increases for same no. of switches used in second method. The following analysis is made to calculate the voltage values, no. of switches required for the extension of n no. of cell connected in cascaded form. In other words, the mathematical form is as shown in below fig12. Now, in this method the voltage source values are not equal, this topology is suitable for PV cell arrays. To exemplify the operation of algorithm , a case study has given as 17-level inverter.

      S1n S2n

      Now, in this method the voltage source values are not equal, this topology is suitable for PV cell sources.

      Number of voltage levels, N levels = 2.3n 1 Number of IGBT switches, N switches = 2n 4 Number of voltage sources, N sources = 2n Variety of voltage sources, N asymmetry =2 n Number of diodes ,N diode = 2n

      Lev el	S1 1	S2 1	S1 2	S2 2	D1 1	D2 1	D1 2	D2 2	T 1	T 2	T 3	T 4
      8	0	1	0	1	0	0	0	0	1	0	0	1
      7	1	0	0	1	1	0	0	0
      6	0	0	0	1	0	1	0	0
      . .
      1	1	0	0	0	1	0	0	1
      0	0	0	0	0	0	0	0	0	1	1	0	0
      									0	0	1	1
      -1	1	0	0	0	1	0	0	1	0	1	1	0
      . .
      -6	0	0	0	1	0	1	0	0
      -7	1	0	0	1	1	0	0	0
      -8	0	1	0	1	0	0	0	0

      D1n

      D1n

      E1n= 3^(n-1)Vdc E2n=(2*3^(n-1))Vdc

      S2

      S1

      +

      S12 S22 V0

      –

      D22

      D12

      E12= 3Vdc E22= 6Vdc

      Table 4: switching sequence for 17-level inverter

      1. CONCLUSION

         In this paper an asymmetrical cascaded multilevel inverter is proposed. This algorithm is applied for getting a 17-level inverter with less number of IGBTs which is very much advantageous as compared to pre-existing topologies. The

         S11 S21

         D11

         D21

         S3 S4

         proposed topology is advantage as compared to existing topologies in terms of number of switches, number of diodes, and number of sources with number of levels generated. The 17-level cascaded multilevel inverter is gives good results in

         E11=Vdc E21=2 Vdc

         Fig.7. Asymmetrical cell voltage configuration for developed topology

         voltage source values is as,

         In CELL-1, E11=Vdc, E21= 2Vdc CELL-2, E12=3Vdc, E22= 6Vdc

         CELL-3, E13= 9Vdc, E23=18Vdc

         .

         .

         dc

         .

         terms of percentage of THD.

      2. REFRENCES

1. Power Electronics Handbook, by Dr P. S. Bhimbra.

2. Babaei, Ebrahim, and SeyedHosseinHosseini. "New cascaded multilevel inverter topology with minimum number of switches." Energy Conversion and Management 50.11 (2009): 2761-2767.

3. Babaei, Ebrahim, Mohammad FarhadiKangarlu, and FarshidNajatyMazgar. "Symmetric and asymmetric multilevel inverter topologies with reduced switching devices." Electric Power Systems Research 86 (2012)

4. E. Babaei and S. H. Hosseini, New cascaded multilevel inverter topology with minimum number of switches, J. Energy Convers. Manage.,vol. 50, no. 11

   dc

   CELL-n, E1n = 3n1.V , E2n=

   2.3n1.V

5. Sepideh Bahravar, Ebrahim Babaei, and Seyed Hossein Hosseini New Cascaded Multilevel Inverter Topology With Reduced Variety of Magnitudes of dc Voltage Sources, 2012 IEEE