A Novel Exponential Pulse-Decay Modulation Multiplier for VLSI Neural

V V V

(13)

differential configuration resistor, as shown in figure. 2.

TN L W

C1 1 2

1 X

1 X

The characteristics of the AC resistance can be obtained by assuming all of the devices are matched and operate in the

V V

and

V2 VX

• . where is a small value,

ohmic region. I1 and I2 are obtained as follows:

represent the voltage drop across the active resistor of

transistor M5 and VX

is the instantaneous voltage at node B.

ITN becomes as indicated below

I K \ W (V V )

(14)

channel MOS transistors having W/L = 5/2 and model

TN L W C1

parameters of VTH = -.75V and KP = 8 A/V².

Using equations (11) and (14) results in

K \ WV V

d L W C1

n

. (15)

d t CTN

rac CTN

Using Laplace transformation, it can be shown that:

S n

(s)

. (16)

S

(a)

The initial condition of n (t) is

(t 0) V

Cc n . (17)

n I N C

TN

Therefore,

Ccn

(18)

n (t)

t VIN C

TN

Q I

dt 1 K\ W (V

V ) dt

(19)

2

2

n M

12 L

GS12 TH

2

2

(b)

GS

GS

V

12

VTH

VX VDD VTH

n (t)

(20)

Figure 4: SPICE simulation results showing the signal outputs on nodes A & B with different weight voltage of: (a) -3V, (b) +3V.

Q 1 K \ W 2 dt

(21)

n 2 L n

The double MOSFET differential resistor is found to be superior in linearity and can be operated under VDS and VTH variations. In the operating region (ohmic), and to avoid more

complications in the system model, there is no physical

justification to multiply 1 VDS with the drain current.

Therefore, since

VDS is so small in that ohmic region and

(a)

has little effect on ID, a transient multiplier characteristic of an EPDM circuit and quadrant multiplier modified synapse circuit has been simulated in Figures 4 and 5. With Vinput of 5 V and Vweight of 0V, the transfer curves of this synaptic circuit for weights from -3 V to +3 V are shown. The DC bias voltages are 5V, -5V, 4V, and -3V for VDD, VSS, VC1, and VC2 respectively.

Both circuits are simulated by SPICE a simulator using N- channel MOS transistors having W/L = 3/5 and model parameters of VTH = 0.75V and KN = 24 A/V², and P-

V. ADVANTAGE OF THE NEW EPDM MULTIPLIER

The modified EPDM circuit has added advantages when compared to the conventional circuit. Because there is no static path between bias voltages it will result in low power consumption when integrated at VLSI levels. It successfully reduced the influences of VDS and VBS by using the double- MOS differential configuration with matched devices operating in the ohmic region, as indicated in Figure 6. The modified circuit not only makes the AC resistor linear, but removes the influence of the bulk-source voltage. The effect of the channel-length modulation has been reduced as all

(b)

Figure 5: SPICE simulation results showing the signal outputs on nodes A & B at M11 & M12, with different weight voltage of: (a)

3V, (b)+3V.

devices are operating at the ohmic region. And, since VDS is so small in this region, it has little effect on ID. Due to neglect of the channel-length modulation and body effects, the output becomes more linear and the THD problem is ignored forever. The die area is small compared to the previous design because the smaller transistor dimensions can be chosen than those in the other circuit.

2

2

Although the linearity of the new circuit is very good over a wide range of input signals, the dependence of output charge

V

V

on S prevents this circuit from being an ideal linear multiplier. The combined trans-conductance (gm) of devices N1-N4 (or P1-P4) must be small enough to ensure a high

equivalent resistance between node B and VDD (or node A

V

V

S

S

and +VDD), to assure good capacitive coupling from \ to

node B (or to node A). It may happen to see an offset in the output due to non-ideal matching between devices in the aspect ratios, parasitic capacitances, and threshold voltages.

IV. PROPOSED EPDM ANN SYNAPSE CIRCUIT

The suggested EPDM multiplier circuit shown at Figure 7 became the more suitable synapse circuit for building the new synapse memory matching cell.

N

N

N

N

The proposed circuit is basically an enhancement EPDM with two or more gates. One of the gates is left floating and other select gates act as the gate of a regular enhancement MOSFET. Referring to Figure 8 and the total current described by equation (22), that controls the ON and OFF states of biological neurons transistors by calculates the weighted sum of all input signals.

Figure 7: Equivalent of the proposed EPDM floating gate circuits

VFGS

FG

N

N

• Ci

  VG i VS

  The operation of the new suggested synapse memory cell

  shown in Figure 9 can be described by equation (23).

  C0

  Cj

  i 1 C0

• Cj

  K V

  *V C

  • K V

    *V C

    \ \

    j 1

    j 1

    V

    1 IN1 W 1 G1 2 IN 2 W 2 G 2

    (23)

    Where FG is the initial charge stored on the floating gate

    out

    CG1

• CG 2

C0

due to the programming process.

I 1 C W (V V )2

DS 2 OX L FGS TH

With two-inputs, one acts as an input vector and the other as a template vector. Each is applied to the corresponding input of its multiplier. The weight signals of each chosen EPDM

multiplier are equal in magnitude and opposite in direction.

(22) 1 C

W (

Ci V

N

N

V V )2

The output of the two matched multipliers is out of phase.

N

N

2 OX L

N

G i

i 1 C0 Cj j 1

S TH

When V1~ = zero, the proposed inverter does not turn on because the floating-gate potential is a little smaller than its inverting threshold. The inverter gives an output of logic 1,

S TH

S TH

K ( Wi VG i i 1

V V )2

which is input to the CMOS inverter.

The CMOS inverter is then activated to give logic 0 outputs. The opposite action of this work is done. When V1~Vn are non-zero signals.

Figure 6: Equivalent of programmed floating gate circuits

Figure 8: The signal voltage at the floating-gate voltage at selected gates inputs (VG1 and VG2).

Figure 9: Simulation results of the suggested synapse-memory cell at input signals VIN1=VIN2=10V and weight signals VW1=VW2=1V

The floating-gate potential of the proposed inverter is larger than its inverting threshold. It turns on and gives logic 0 output that turns off the CMOS inverter. The CMOS inverter gives an output of logic 1.

As shown at Figure 9, the results are accumulated on the MOS floating gate and the result is the difference between them.

The output illustrates either logic 1 or logic 0, according to the degree of matching between inputs.

1. ANALYSIS OF THE PROPOSED synapse memory cell

   The proposed circuit has been utilized to produce the sum operation with no dc-current flows. As a result, a dc-current free operation of the cell has been established making it possible to build a low power system. The circuit is very simple in concept and constrution. It consumes a small chip area because there are no switches, as in most classical matching cells. The proposed synaptic memory cell design with floating-gate potential and real-time monitored during data writing achieves accuracy and high speed for analog voltage storage through the thresholding action of proposed inverter.

   Because no complicated control circuitry is required for weight updating, the new version cell allows high-density integration of a synapse cell as well as a high-speed learning operation of a proposed self-learning neural network. The static power dissipation in each inverter is zero in both of its states, where the dissipation due to the leakage currents is so small as to be neglible.

   A low-resistance path exists between the output terminal and ground or VDD. These low resistance- paths ensure the output voltage is independent of the exact values of W/L ratios or any other device parameters. Furthermore, the low-output resistance makes the inverter less sensitive to the effects of noise and other disturbances.

   V. CONCLUSION

   S

   S

   The proposed multiplier can modulate an input signal based on a locally stored weight voltage. The modified EPDM multiplier circuit can produce efficient computations in the analog domain with a reduction in power and area requirements. Although the linearity of the new circuit is very good over a wide range of input signals, the dependence of output charge on V2 prevents this circuit from being an ideal

   linear multiplier. The average actual power consumption of the new circuit will be less when compared to a conventional EPDM circuit. The combined trans-conductance (gm) of devices N1-N4 (or P1-P4) must be small enough to ensure a

   high equivalent resistance between node B and VDD (or node A and +VDD) to assure good capacitive coup- ling from V\ to

   S

   S

   node B (or to node A). There is a possibility of appearance of an offset in the output due to less than ideal matching between devices in the aspect ratios, parasitic capacitances, and threshold voltages.

   Practically, I observe that the output of the proposed matching cell is not exactly zero. This is due to the non-perfect matched device parameters and the parasitic capacitance coupled to the floating gate.

   The speed of operation of a digital system as a computer is determined by the propagation delay of the logic gates used to construct the system. To obtain lower propagation delay and faster operation, a higher process transconductance parameter should be utilized and the transistor W/L ratio increased. There are design tradeoffs because these conditions increase the dynamic power dissipation.

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Dr. Raed Althomali was born in Saudi Arabia, in 1979. He received the B.S. and Electrical engineering from the Yanbu Industrial College, SA in 2008 and the

M.S. and Ph.D. degree in Electrical and Computer engineering in fiber optics and photonics from SIU, Illinois in 2014.

He currently is the Managing Director, Yanbu English Language & Prep Year Institute, Saudi Arabia. His main areas of research interest are signal processing, all- optical devices, VLSI, active filters, and neural networks. Dr. Raed is a member of the Saudi Council of Engineers and Optical Society of America.