A Novel FGMOS Voltage Reference with Temperature and Power Supply Compensation

A Novel FGMOS Voltage Reference with Temperature and Power Supply Compensation

A Novel FGMOS Voltage Reference with Temperature and Power Supply Compensation

G. Sambasiva Rao, B. Rama Rao

Amrita Sai Institute of Science and Technology, India

Abstract

In this paper, we propose a scheme for generating a reference voltage which can be implemented in the CMOS technology. The system performance is investigated for a range of supply voltages and temperature. The system performance is improved by the use of floating gate MOSFET. The work includes mathematical modeling of the proposed voltage reference circuit and its verification by simulation using TANNER EDA tools. The circuit performance over temperature and supply voltage is better than the prior works in this area. The reference voltage is obtained by combining the weighted VGS difference with weak-inversion VGS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 458mV, temperature coefficient of 10 ppm/oC in [20oC ~ 120oC ] at a 0.8 V supply voltage. The line regulation of the reference voltage is 5.6mV/V when the supply voltage is increased from 0.8 V to 2 V.

1. Introduction

   source voltage of a MOSFET, biased with a fixed drain current, decreases with temperature in a quasi-linear fashion. Starting from this observation, a gate-source voltage can be used instead of a base-emitter voltage to design a voltage reference independent of temperature. Many researchers have proposed several low-power and low-voltage reference circuit solutions based on weak-inversion MOSFETs [2],[3]. The effect of temperature in the weak inversion characteristics of MOSFETs is discussed [4]. In this paper, a low temperature coefficient FGMOS voltage reference circuit is presented. The reference circuit generates the voltage with positive temperature coefficient from weighted VGS difference between two NMOSFETs in the weak inversion region while the voltage with negative temperature coefficient is obtained by the weak inversion VGS voltage. With the MOSFETs operating in the weak inversion, the reference circuit consumes less current and thus reduces the power consumption.

   The floating mosfet is presented in section 2, proposed voltage reference circuit is illustrated in section 3. Simulation results are presented and compared with previous work in Section 4. Section 5 concludes the paper.

2. Floating Gate MOSFET

   A Floating Gate MOS Transistor consists of a conventional MOS transistor with its gate surrounded by SiO2 and capacitively coupled to multiple controlling input gates [11]- [14].Since the gate surrounded by SiO2 has no DC path to a fixed potential, it is known as Floating Gate. ie, The floating gate is formed by the first polysilicon layer, while the multiple-input gates are formed by the second polysilicon layer located above the floating gate. The conduction of the FGMOS transistor is different from that of conventional MOS transistor having the same terminal potential, due to the capacitive coupling between the Floating Gate and control gates. When a voltage is applied to the control gates, capacitive coupling between the control gate and Floating Gate induces an electrical field on the Floating Gate (FG). The induced field on the Floating Gate modifies the conductance of underlying channel region.

   A two input Floating Gate MOSFET is shown in Fig.1 where a dc voltage (Vb) is applied at one of the gates called bias gate (BG) while the signal is applied at second gate termed as signal gate (SG).

   The resultant threshold voltage VT ( fg ) of the FGMOS [8] with respect to signal gate, depends on the threshold voltage of the Floating Gate (VT ) and is given in (1).

   V V k

   The proposed voltage reference circuit is shown in Fig. 2. Transistors M1 and M2 are connected as a FGMOS current mirror and served for realizing the function of self-biasing. The current mirror of M1 and M2 is designed to make

   VT ( fg )

   T T 1

   k1

   (1)

   MOSFETs M3 and M4 operate in the weak inversion such that the voltage across R1 is proportional to the absolute temperature (PTAT). Hence, the resistor ratio R2/R1 can be used to compensate for the variation of the gate-source voltage of M4 with respect to the temperature.

   For an n-MOSFET operating in the weak-inversion region, with the condition of VDS 3VT, its drain current can be given as[5],[6]:

   I W I

   D L t

   exp( VGS

   nV

   Vth )

   (2)

   Fig.1. Two input Floating Gate MOSFET structure

   where It

   qXDn

   N qo

   exp( VT

   T

   ) , Vth

   is the threshold

   Where k1 c1 cT k2 c2 cT , C1 and C2 represent the capacitances between floating gate and control gates respectively, CT is the sum of all the capacitances between control gates and floating gate, capacitance between floating gate to drain, capacitance between floating gate to source and capacitance between floating gate to bulk.

   voltage, n is the subthreshold slope factor, X is the thickness of the region in which ID flows, Dn is the diffusion constant for electrons, Nq0 is the equilibrium concentration of electrons in the substrate, VT = kT/q is the thermal voltage, and C is a constant.

   The drain current of M3 and M4 can be expressed as

3. Proposed Voltage Reference

   I D3

   K3 I t

   exp VGS3

   nVT

   Vth

   (3)

   I D4

   K 4 I t

   exp

   VGS3

   nVT

   Vth

   (4)

   where Ki = (W/L)i and K3=NK4. Using (2) and (3) assuming that the ratio of K1 and K2 is unity which means that the current flowing into M3 and M4 are equal, we can obtain

   VGS 4

   VGS 3

   nVT ln( N )

   (5)

   From Fig. 1, the two gate-source voltages of M3 and M4 are also related by

   VGS 4

   VGS 3

   I D3 R1

   (6)

   Substituting (4) into (5), we obtain

   I D3

   VGS 4

   VGS 3

   R1

   nVT ln( N )

   R1

   (7)

   (6) shows that the drain current of M3 is proportional to the absolute temperature(PTAT). The gate voltage VS of M3 and M4 is given as:

   Fig. 2. Schematic of proposed voltage reference circuit.

   VS VGS 4 2I D3 R2

   (8)

   For an n-MOSFET with PTAT drain current, we can obtain the expression of VGS from (1):

   R3

   R

   Vref 1 VS

   4

   (14)

   VGS

   I D

   nVT ln W

   I

   L t

   Vth

   (9)

   Substituting (8) into (5), we obtain

   T

   V nV ln

   I D3

   V I R

   (10)

   GS 4

   K3 It

   th D3 1

   With the source and bulk terminals connected together, we could have the expression of Vth as follows [6].

   Vth

   2qN A (2 f )

   2 f

   Cox

   Qss

   C

   ms

   ox

   (11)

   Because ms , QSS, and COX are independent of temperature, differentiating (10) gives

   dVth dT

   1 Eg

   T0 2q

   f 2

   2

   f

   (12)

   Fig. 3. Reference voltage against supply voltage

   where NA is the doping density, is the permittivity, f is the Fermi level, COX is the gate oxide capacitance, ms is the work function difference existing between the gate metal and the silicon, QSS is the positive charge density existing in the oxide at the silicon interface, Eg is the band gap of silicon at T =0°K,

   and is defined as[6]

   1

   Cox

   2q N A .

   Equation (11) shows that the threshold voltage reduces with the increase of the temperature since f < Eg/2q. Thus, we could say that the threshold voltage Vth has a negative temperature coefficient. Substituting (6) and (9) into(7), the voltage VS can be expressed as

   V nV ln

   I D3

   V I R

   2I R

   K

   I

   S T

   3 t

   th D3 1

   D3 2

   I nV ln( N )

   Fig. 4. Reference voltage against temperature at supply voltage.

   T

   nV ln

   D3 V T (R

   2R )

   th

   1 2

   parameter	Proposed work	Previous Work[5]
   Minimum supply voltage	0.8V	1.5V
   Reference voltage	458mV	580mV
   Temperature coefficient	10 ppm/ C	62 ppm/ C
   Line regulation	5.6mV/V(0.8V~2V)	8mV/V(1.5V~3V)

   K3 It R1

   TABLE

   1.COMPARISON WITH PREVIOUS WORK

   nVT ln

   nVT ln( N )

   K I R

   V th

   nVT

   ln( N ) R1

   2 R2

   R

   (13)

   3 t 1 1

   Hence, the size K3 of M3, the resistor ratio R2/R1, and the

   aspect ratio N of M3 and M4 can be designed to make the temperature coefficient of VS equal to zero at a selected

   temperature. Therefore, the final output reference voltage Vref

   can be expressed as

4. Simulation Results

   Fig. 3 shows the simulation result of the reference voltage Vref against supply voltage at room temperature. The circuit is simulated using TANNER EDA tools with BSIM 4.4 model . The reference voltage is independent of supply voltage when the supply voltage Reaches near 0.8V. The line regulation is

   5.6 mV/V when the supply voltage is increased from 0.8V to 2V.The temperature coefficients of the reference voltage Vref against temperature is obtained 10ppm/ C at 0.8V supply voltage. Fig. 4 shows the simulation results of the reference voltage Vref against temperature supply voltage. Table 1 shows comparison of proposed work with previous work [5] in terms of reference voltage, temperature coefficient and line regulation.

5. Conclusion

A low-power, low temperature coefficient FGMOS voltage reference circuit with MOSFETs operating in the subthreshold region is presented. The voltage reference is also independent of supply voltage 0.8V and temperature. Simulated reference output voltage is around 458mV and the minimum supply voltage is 0.8V. The temperature coefficient is 10ppm/ C from 20 C~120 C and the line regulation is 5.6mV/V from 0.8V to 2V. The circuit has been simulated using TANNER EDA tools with BSIM 4.4 model.

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