A Study and Comparison of Cascaded Multilevel Inverters using GATES for Switching

A Study and Comparison of Cascaded Multilevel Inverters using GATES for Switching

Mr. Kalyan Dadhirao

Electrical Engineering Department Veermata Jijabai Technological Institute, Mumbai, India.

Prof. Mrs. J. O. Chandle

Electrical Engineering Department Veermata Jijabai Technological Institute, Mumbai, India.

Abstract With the advent of high power drives in industries, high voltage motors are to be driven with the help of inverter. For this multilevel inverters are used instead of conventional inverters. This paper presents a study and comparison of seven level and seventeen level cascaded H-bridge multilevel inverter.

S1 S2

VA

VN

S3 S4

Vdc

+

SDCS

–

For analysis and verification, MATLAB/SIMULINK models are modeled. Simulink models are simulated and analyzed to derive conclusions. The total harmonic distortion (THD) is used to compare the results.

Index Terms Multilevel inverters, Cascaded, H-bridge, Simulink model, and Total Harmonic Distortion.

1. INTRODUCTION

   Wide ranges of high power drives are used in industries, which require continuous power supply. At the time of power

   VN-1

   VTOTAL

   V1

   S1 S2

   S3 S4

   S1 S2

   S3 S4

   Vdc

   Vdc

   +

   SDCS

   –

   +

   SDCS

   –

   failure they are operated with D.C supply. For this purpose we need DC to AC converters. Conventional inverters have a

   lot of drawbacks like high switching losses, increased stress N

   on switches, high harmonic content etc. For solving this

   problem H-bridge inverters are used. They are connected in

   series to get stepped and better output [1]. Hence the study and betterment of multilevel inverters is necessary.

   S1 S2

   S3 S4

   Vdc

   +

   SDCS

   –

   In this work, the cascaded multilevel inverters are studied and compared based on harmonic contents. For this, five level, seven level and seventeen level inverters are modeled in Simulink to get the clear picture of improvement in output voltage waveform with increase in number of levels. Fourier analysis is done to get the percentage of total harmonic distortion present in the output.

2. STUDY OF CASCADED MULTILEVEL INVERTER The multilevel cascaded inverter is the best alternative

   over conventional inverters. It is very suitable for medium

   voltage motor drives and utility applications [3]. Fig 1 shows a generalized model of single-phase cascaded H-bridge multilevel inverter.

   Fig.1. Single phase cascaded H-bridge multilevel inverter.

   There are n bridges in fig1. Each bridge has four switches and an individual D.C source. The bridges are cascaded to get different voltage levels. In this paper we will study five, seven and seventeen level cascaded H-bridge inverter. The switches in each leg of each bridge are complimentary in nature such that short circuit doesnt take place.

   The models proposed in this paper are single-phase multilevel inverters. They give stepped output as per the switching frequency and switching design of the gates [4]. The switches are strategically switched to get an output that resembles a sine wave. More the number of steps more close the output is to sine wave, lower the harmonic content, better is it for the machines.

3. MATLAB SIMULATION

   1. The Network and Working Model of 5/7 Level Inverter

      Working of cascaded H-bridge inverter along with its figure and explanation is already being discussed. In this paper, now we will see a model in which two H-bridges are used and a five level and seven level output is obtained. Fig 2 below shows the desired model.

      S1 S2

      VA

      S3 S4

      Vdc

      +

      SDCS

      –

      VTOTAL

      N

      S1' S2'

      S3' S4'

      Vdc

      +

      SDCS

      –

      Fig 3: Matlab model simulated for the above system using gates for switching

      Fig2: Five level inverter and seven level inverter model with two H-bridges cascaded.

      For the five level output from the model we keep both voltage sources equal. In this case both the D.C. Sources are kept at 24V. And for getting seven level output one of the

      D.C. sources is kept as double of the other to get one extra level of output. In this case the output so achieved has seven levels.

      The MATLAB model for the above network is shown in the next fig 3. The switching pulses are obtained by giving signal to the discrete monostable flip-flop, which gives a pulse of a desired duration. These pulses are then passed through XOR gates where they are processed to get the final gate signals. These gate signals are given to sub-system 2. Now for the subsystem 1 pulse generator signals are sent to AND gate which processes the signal and gives the desired outputs. These outputs are used as gate signals for subsystem 1.

      Fig 4: Sub-system 1 for the above SIMULINK model

      The above fig 4 shows sub system 1. It can be seen that two gating signals are received from the AND gates. Two connections leave the subsystem, one is connected to the load and other is connected to voltage measurement unit; which is further connected to the scope for final output view.

      Fig 5: Sub-system 2 for the above SIMULINK model

      The above figure 5 shows us subsystem 2 model. The gating signals are obtained from the XOR logical operators. Two connections are leaving the subsystem one is connected to load and other is connected to the voltage measurement unit to give final waveform in the scope.

   2. Waveform for Switching and Final Waveform FOR FIVE LEVEL OUTPUT:

      The same network can be used to get both five and seven level output. The switching is done strategically to get the output as desired. The switching sequence and the co-related switches are tabulated and the output voltage than obtained is also shown in the table 1. This is followed by the graph showing the exact switching and final waveform

      Sr. No.	Operating switches	Operating GATES	Output Voltage
      1	None	None	0 V
      2	(S5,S8)	AND1	24 V
      3	(S1,S4)	XOR1	24 V
      4	(S1,S4), (S5,S8)	XOR1 ,AND1	48 V
      5	(S6,S7)	AND2	-24 V
      6	(S2,S3)	XOR2	-24 V
      7	(S6,S7) ,(S2,S3)	XOR2 ,AND2	-48 V

      Table 1. Switching sequence for the five level output

      Fig 6: Switching and final waveform for five level inverter

      FOR SEVEN LEVEL OUTPUT

      The same network is now used to get seven level output. The switching sequence for the seven level output along with tabulated data for the switching and output waveform is given below. This followed by the output of the cascaded multilevel inverter.

      Sr. No.	Operating switches	Operating GATES	Output Voltage
      1	None	None	0 V
      2	(S5,S8)	AND1	24 V
      3	(S1,S4)	XOR1	48 V
      4/p>	(S1,S4), (S5,S8)	XOR1 ,AND1	72 V
      5	(S6,S7)	AND2	-24 V
      6	(S2,S3)	XOR2	-48 V
      7	(S6,S7) ,(S2,S3)	XOR2 ,AND2	-72 V

      Table 2. Switching sequence for the seven level output

      Fig 7: Switching and final waveform for seven level inverter

   3. Seventeen Level Inverter Model

      Fig 8: Seventeen level cascaded multilevel inverter

      Fig 9: Subsystem for the seventeen level cascaded multilevel inverter

      The seventeen level inverter model has been prepared for analysis. It has total 8 H-bridge cascaded back to back, as shown in the MATLAB model. Each subsystem has 4 switches; here we have used IGBT for switching. The D.C Source voltage for each bridge is taken to be 1V, for testing purpose. IGBTs in each leg are complimentary to each other to avoid short circuit.

      When the above model is simulated in SIMULINK and compared to a sinusoidal wave of magnitude of 8V (peak) we get the final output in the form as shown below.

   4. Final Output Waveform

   Fig 10: Output waveform

4. FOURIER ANALYSIS FOR THE OUTPUT

   WAVEFORM

   The line to line RMS voltage can be found by the equation.

   = = 0.8165

   The RMS of nth component line voltage is

   For n=1, represents the fundamental rms line voltage

   = 0.7797

   The rms value of the line to neutral voltage i.e. phase voltage can be found from the line voltage component

   =

5. SIMULATION RESULTS

   The simulation is performed on the multilevel inverter models. And FFT analysis is done on five level, seven level and seventeen level inverter models. The results indicating the percentage of total harmonic distortion along with the number of harmonics present in the output are shown below. Each harmonic is indicated in the graph below. This is shown as a percentage of the total output voltage. As we increase the level of inverter the percentage of the fundamental frequency component increases and the harmonic content decreases which is eminent in the graph.

   Fig 11: The FFT analysis for output waveform of five level cascaded inverter.

   =

   = 0.4714

   The output THD component can be found from the equation

   Using the FFT analysis function in MATLAB/SIMULINK can directly do this analysis. This gives us the evaluation of the total harmonic distortion in graphical form.

   Fig 12: The FFT analysis for output waveform of seven level cascaded inverter

   Fig 13: The FFT analysis for output waveform of seventeen level inverter

   It is found that the THD for five level inverter is 30.95%, the THD for seven level inverter is 21.61%, and the THD for five level inverter is 13.74%. thus we can see there is a gradual reduction in THD as we increase the levels of the cascaded inverter.

   REFERENCES

   1. Jose Rodriguez, Jin-Sheng Lai and Fang Zheng, Multilevel Inverters: A survey of topologies, Control applications, IEEE transactions on Industrial Electronics, Vol.49, No. 4, pp. 724-738,August 2002

   2. J. S. Lai and F. Z. Peng, Multilevel converters A new breed of power converters, IEEE Trans. Ind. Applica, vol. 32, no. 3, pp. 509- 517, May/June 1996.

   3. L. M. Tolbert, F. Z. Peng, and T. G. Habetler, Multilevel converters for large electric drives, IEEE Trans. Ind. Applica.,

      vol.35, no.1, pp. 36-44, Jan./Feb.1999

   4. K. A. Corzine, M. W. Wielebski, F. Z. Peng, and J. Wang,Control

   of Cascaded Multilevel Inverters, IEEE Trans. power electron, vol.19, no.3, pp. 732-738, May 2004.

   Kalyan Dadhirao, born in Nagpur, received B.E. degree from RCOEM, Nagpur affiliated to Nagpur university and pursuing M.tech (power system) from Veermata Jijabai Technological Institute, Mumbai. His fields of interest consist of power electronics, drives, and power electronics for transmission.

6. CONCLUSION

As we increase the level of inverter we see that the THD is significantly reduced, this is good as it reduces the ripples in the output. So as we go on increasing the level of inverter towards infinity we get a better sinusoidal wave, but as we increase the level cost of inverter also increases. So it is necessary to insure that we get a better and smother waveform for lower level inverters also.

Cascaded multilevel inverters are thus found to be very suitable for the medium voltage drive operation. Higher level inverters provide better performance as compared to lower level inverters.

Prof.J.O.Chandle, M.Tech in control system is presently associate professor in Veermata Jijabai Technological Institute, Mumbai. Her field of interest consists of Control Systems & Power Electronics.