Analysis of parasitic components in the PWM Inverter in an Electric Vehicle

DOI : 10.17577/IJERTV2IS90671

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Analysis of parasitic components in the PWM Inverter in an Electric Vehicle

Tarun Varma Landa Andrew Moore

School of Electrical Sciences Lead Engineer, WMG IIT Bhubaneswar University of Warwick

Abstract

This Paper describes the effect of parasitic elements in a PWM Inverter used in a vehicle to power the 3-Phase motor. The Mosfet model for high frequency operation and de-coupling capacitor model with the parasitic elements is also discussed. The output waveforms were analysed and the causes for the high frequency ripple in the Voltage and Current waveforms at high switching frequencies in a vehicle are discussed. A spice model is proposed for the inverter circuit by including the parasitic elements in the circuit. The simulation results are verified with the actual waveforms.

Index Terms: PWM Inverter, Power Mosfet, Parasitic Elements, Decoupling capacitor, Spice simulation

    1. Introduction

      Designing DC/AC inverters for vehicular application are gaining renewed attention. PWM inverters are widely used in vehicles for driving the 3- phase AC motors. The basic design is as shown in the figure.1 below. The Switches (or IGBTs, Power Mosfets) receive gate signals from PWM wave generator and connected so as to produce 3-phase voltage and current waveforms.

      Figure.1

      These designs are realised by using a DC link capacitor to minimize the noise that may affect the DC power supply. A perfect capacitor isolates the DC power supply from the ripple content produced in the circuit. However, the components in the circuit are non-ideal. The parasitic elements cause high frequency ripple and overshoot in the voltage and current waveforms which may affect the power supply in the vehicle. This paper describes the various parasitic elements that might cause the ripple. A SPICE model of the circuit is proposed. The results from the spice simulation are compared with the practical results obtained during the operation of inverter in the vehicle.

    2. Background Problem

The PWM inverter that was designed for the vehicle was tested and the waveforms of current and voltage at DC link capacitor were observed to contain a high frequency ripple. The voltage waveform contained overshoot of up to 40v above the DC supply and at a very high frequency. A spice model of the inverter was proposed and the simulation results were compared with the experimental waveforms. As the simulation model is comprised of ideal components, the waveforms did not contain any high frequency content or overshoot. So, the frequency content of experimental waveforms were analysed by Fast Fourier Transform. The analysis showed that the waveform consists of operating frequency along with the harmonic content. The operating frequency is the switching frequency of the PWM inverter. The reason for the harmonic content in the circuit has to be found. The harmonic content is in the range of several KHz which suggests that this is not caused by the motor which runs at 1000-1500 rpm. The parasitic elements which are not included in the spice model can be the real cause. So, the Spice model

of practical inverter with parasitic elements was proposed.

    1. Power Mosfet model

      A really useful MOSFET model which would describe all important properties of the device from an application point of view would be very complicated. On the other hand, very simple and meaningful models can be derived of the MOSFET transistor if we limit the applicability of the model to certain problem areas. The figure (Fig.2) shows a Mosfet model proposed for the inverter.

      Figure.2 MOSFET Model

      The parasitic inductances were included along with the parasitic capacitances. The Mosfet packages may have a very low parasitic inductance (order of nH) due to the pins but when this is connected in a circuit, the external inductance in the circuit in the order of micro henry will have significant effect on the mosfet characteristics especially at high operating frequencies. The load inductance connected at the drain-source junction also affects the characteristics of the mosfet. The parasitic capacitances and inductances cause LC oscillations at high frequencies in the circuit during switching operation.

    2. Decoupling capacitor Model

      The de-coupling capacitors are used to isolate the

      DC power supply from the rest of the circuit. Thus, it protects the DC power supply from voltage spikes and high frequency ripples. But unfortunately, the capacitors are not ideal. All real world capacitors have parasitic components similar to the power supply leads: inductance and resistance. It means that the capacitor can be actually modelled by a series RLC circuit as shown in the figure (Fig.3). The capacitor actually behaves as an inductor at high frequencies (higher than the self-resonant frequency). The ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance) depend on the wires connected to the capacitor plates and the type of package. When the cable wire parasitic elements add to this, the resistance and Inductance become significant. The leakage resistance depends on the type of dielectric used.

      Figure.3 Capacitor Model

      Inverter circuit simulation:

      A spice model was developed by replacing the ideal components with the more practical components (mentioned above).The complete circuit for the inverter is shown in the figure (Fig.4). The inverter design is slightly modified from the basic design for better performance.

      Figure.4 CIRCUIT

      A simple model for 3-phase motor is used for simulation purpose. The Mosfets are triggered by a signal from the PWM generator. The switching frequency of the PWM wave is in the order of KHz. The circuit for PWM wave generator is shown in the figure (Fig.5).

      Simulated DC link Voltage (See the Voltmeter in circuit Diagram)

      Vsin

      Vtri

      Vdc

      Figure.5

      (See the

      RESULTS:

      The proposed spice model was simulated with 250V DC input. The voltage and current waveforms at DC link capacitor were plotted and compared with the actual plots obtained from the vehicle (Test Condition: Wide open Throttle).

      The waveforms in the figures look similar but the similarity can verified only after analysing the frequencies contained in the waveforms. The frequency content of the above waveforms is verified by the Fourier analysis. The FFT plots of the waveforms are shown below.

      Measured Current at DC link capacitor (See the ammeter in circuit Diagram)

      Simulated Current at DC link capacitor (See the ammeter in circuit Diagram)

      gram)

      FFT Plot of Measured Voltage

      AM1

      AM1

      Figure.6

      The FFT analysis of current and voltage show the same frequency content in the signal as seen in the plots. When the parasitic elements of the Mosfet are removed, the harmonics in the FFT plot vanish. This proves that the harmonic content in the current and voltage signals is caused by the Mosfet parasitic elements. If the DC link capacitor is ideal, then it would completely eliminate the ripple and overvoltage in the current and voltage waveforms respectively. So, the capacitor is made more practical by including the parasitic elements.

      Equivalent circuit Simulation:

      The equivalent circuit for one mosfet of the inverter was simulated to analyse the behaviour. Figure.8 shows the equivalent circuit. The circuit was switched at a 10 KHz frequency. The voltage and current at the DC link capacitor were measured and the FFT plots were obtained as shown in the figures. There are many harmonics in the plot caused due to the parasitic elements.

      FFT Plot of Simulated Voltage

      R2 C2

      +

      +

      VG1

      L4 R5

      T1

      T1

      R3

      R3

      Figure.8

      L2

      L2

      C1

      C1

      VG2

      L3

      R1

      R1

      R4

      R4

      + A

      L1

      L1

      +

      +

      +

      +

      VS1

      FFT Plot of Measured Current

      Equivalent Circuit for one Mosfet of the Inverter

      Figure.7

      FFT Plot of Simulated Current

      Figure.9

      FFT Plot for Voltage FFT Plot for Current

      frequency ripples that are caused by the parasitic elements.

      Figure.10

      It can be observed that the FFT plots in figures 6 and 7 can be obtained by extrapolating (combining the graphs of all mosfets) these plots in Figure.9 and 10. So, if we analyse the cause for these harmonics, we can explain the behaviour in the FFT plot for the complete inverter. So, Mathematical analysis is done for the equivalent circuit.

      Mathematical analysis of Equivalent Circuit:

      The equivalent circuit was developed to analyse the cause of the harmonics that can be seen in the frequency plot. Mathematical analysis was done to understand the resonance of the circuit. The relation obtained was a 6th order polynomial.

      =0

      w in the equation has 3 real solutions. So, the circuit has 3 resonant frequencies. These resonant frequencies are the peaks seen in the figures 9 and 10. When the parasitic elements are removed, the mathematical relation is a 2nd order polynomial which has complex solutions. So, no resonance occurs in the circuit on removing the parasitic elements. So this analysis proves that the parasitic elements of the circuit are the cause for the high frequency voltage and current ripples at the DC link capacitor of the inverter.

      Conclusion:

      The proposed inverter model with Power Mosfet and Decoupling capacitor along with the parasitic components allow for more accurate modelling of over voltages and high DC current ripple at the DC-link capacitor. The switching frequency of PWM generator causes the peak at 10 KHz in the plots and the parasitic elements of the Mosfet and DC link capacitor are responsible from the harmonic content. So, the proposed model for the inverter can be more practical Spice model. The effect due to the parasitic elements has to be eliminated to protect the power supply from high DC current ripple and over voltages. Damping circuits should be used to eliminate the high

      Acknowledgment:

      This work is being published as a part of 1st

      authors research internship at WMG, University of Warwick, UK. WMG is a part of the HVM Catapult

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