Comparative Analysis of Self-Controllable Voltage Level (SVL) and Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45 Nanometer Regime

Comparative Analysis of Self-Controllable Voltage Level (SVL) and Power Gating Leakage Reduction Techniques Using in Sequential Logic Circuit at 45 Nanometer Regime

Bhanupriya Bhargava1, Pradeep Kumar Sharma2, Shyam Akashe3

1Research scholar, ECED, ITM, Gwalior, India 2Research scholar, ECED, ITM, Gwalior, India, 3Associate Professor. ECED, ITM, Gwalior, India

Abstract

Today leakage power has become an increasingly major issue in low power VLSI design. With the most important element of leakage, the sub-threshold current, exponentially increasing with decreasing device dimension, leakage commands associate ever increasing share in the processor power consumption. In this paper two techniques such as power gating and self controllable voltage-level (SVL) circuit for reducing leakage power in sequential circuits are proposed. This work analysis the power and delay of three different types of D Flip-flops using pass transistors logic, transmission gates and gate diffusion input (GDI) CMOS design style. All the circuit parameters are simulated with and without the application of leakage reduction techniques. All these proposed circuits are simulated with and without the application of leakage reduction techniques. The circuits are simulated using Cadence Virtuoso tool at 45nm technology for various parameters

Keywords: Pass Transistors Logic, Transmission Gate, GDI, Self-Controllable Voltage Level (SVL) technique, Power Gating.

1. INTRODUCTION

   CMOS technology has been scaling down to meet the performance, production cost and power requirements of the industry [1]. With the rapid growth of transportable electronic devices, low power design is crucial in the design of electronics. Therefore, the main focus of the industry has modified from high performance designs to low power designs to meet the demands of the transportable electronics. Since the battery period is a key factor for a portable device, both the electronic industry and the battery industry have been attempting to address this need [3] [4]. However, power reduction is also an issue in high performance computers where heat dissipation has become a major bottle neck in keeping the processors at proper operating temperatures [5]. This is due to the growing power per unit area as a result of the reduction in the minimum feature size of the process technology, which allows a designer integration of transistor with higher speeds in each chip. During this paper we design and analysis of various style approach D flip-flop

   circuits using with Stacking power gating and SVL leakage reduction techniques.

   This paper is organized as follows: in Section 2 describes self controllable voltage- level (SVL) and power gating leakage reduction techniques that are applied to the proposed designs. Section 3 presents three different designs of D flip-flops using pass transistor logic, transmission gates and Gate-Diffusion Input (GDI) gates. Section 4 presents the simulation and results of the flip-flops and section 5 gives the conclusion.

2. CMOS IMPLEMENTAATION OF D FLIP-FLOP CIRCUITS

   The flip-flops are basic memory storage element in digital circuits that store one bit information [9]. This section presents the three different design style of CMOS technology which is used to implement the D flip-flops circuits. These proposed circuits are combined pair of master and slave D latch circuit. The wide use of sequential logic and memory storage systems in modern electronics results in the implementation of low power and high speed

   design of basic memory elements. One of the most important basic memory elements is the D flip-flop (DFF). Three different designs of D flip-flops in CMOS logic are presented in this section. The D flip-flop combines a pair of master and slave D latch. Design I uses pass transistors logic (PTL) and inverters for the master-slave latches [10] as shown in Fig. 1. The two chained inverters are in memory state when the PMOS loop transistor is on, that is when clk

   = 0.Other two chain inverters on the right hand side acts in the opposite way.

   ,when the clk signal is high and internal values are maintained due to conduction of the NMOS transistors. The inverters are responsible for maintaining the complementary values of the internal signals and the circuit outputs.

   VDD

   Q

   QBAR

   The flip-flop changes its state during the falling edge of the clock. Fig 2 shows the design

   II that uses transmission gates (TG) and inverters [11]. Transmission gate is an important structure implemented using CMOS integrated circuit that sustains switch function, efficient layout and logic reduction. PMOS and NMOS transistors are used to implement this solid state switch. Transmission gate and inverters are utilized to implement D flip flop as illustrated in Figure 2 shows. At the negative edge of the clock period, transmission gates T1 and T4 are ON and transmission gates T2 and T3 are OFF. During this time the slave maintains a loop through two inverters P3, P4 and T4. Currently the previous triggered value from Din is stored

   DIN

   CLK

   GND

   Fig.1. D flip-flop using Pass transistors

   VDD

   P1 P2 P3 P4

   Q

   QBAR

   in the slave. At the same time master latches next state but as T3 is OFF it is not passed to slave. At the positive clock edge T2 and T3 are turned ON and the new latched value passes to slave through the loop of two inverters P1, P2 and T2. Fig. 3 shows design III with master-

   DIN

   T1

   T2

   CLK

   T3 GND

   T4

   slave connection of two GDI D-latches [13]. The power dissipation is optimized by GDI technique and reduces the number of transistor. For two-transistor implementation of logic functions and restoration of in-cell swing within certain operation conditions, GDI technique offers unique advantage for low power design techniques. Representation of two GDI based latches connected as master-slave configuration is illustrated in Figure 3. In this the body gates are responsible for the state of the circuit. These gates are controlled by the control signal i.e. clock (clk) signal and create two alternative paths. One for transparent state of the latch

   ,when the clock is low and the signals are propagating through PMOS transistors .The other one is for the holding state of the latch

   Fig.2. D flip-flop using transmission gates

   VDD

   DIN

   CLK Q

   QBAR

   GND

   Fig.3. D flip-flop using GDI gates

3. PROPOSED LEAKAGE REDUCTION

   TECHNIQUES

   In this section two leakage reduction techniques namely transistor stacking and self-controllable voltage level circuit that are applied to the above

   Upper SVL Circuit

   VDD

   CL

   PMOS

   NMOS

   NMOS

   Load Circuit

   In

   VDD

   Out

   CL

   PMOS

   VDD

   Upper SVL Circuit

   NMOS

   NMOS

   circuits are described.

   1. Self-Controllable Voltage Level (SVL) Circuit for Low Power, High Speed CMOS Circuit

      Load Circuit

      In Out

      Lower SVL Circuit

      NMOS PMOS

      CLB

      PMOS

      Load Circuit

      In Out

      Lower SVL Circuit

      The SVL technique is used to minimize the leakage power of the circuit. Three types of

      VSS VSS

      CLB

      NMOS PMOS

      self controllable voltage level circuit these are Upper SVL, Lower SVL and combination of both upper and lower SVL circuits have been proposed in this paper [12]. The figure 4 shows

      Fig.4 (a) Upper SVL

      circuit

      Fig.4 (b) Lower SVL

      circuit

      VSS

      PMOS

      Fig 4 (c) SVL

      ircuit

      all these proposed SVL techniques which are applied on CMOS inverter for simplicity of explanation of the SVL circuit function. The circuits are operated in both operation modes which is Active mode and standby mode. When our circuit is working inactive mode at that time CL= 1 and CLB = 0. So our circuit will get maximum supply voltages and circuit will work in proper manner. When our circuit is working in standby mode at that time the value of CL =

      0 and CLB = 1. So due to series connection of transistors, the value of VD (Virtual Ground) will be minimum as compared to VDD due to voltage drop. Same phenomenon is also occur in the Lower SVL circuit. Due to voltage drop the value of Vs will be greater as compared to Vss. Finally it is said that by using this technique the overall voltage of the circuit will be minimum. And when the circuit works on minimum voltage the leakage power is also reduced. The upper SVL circuit consists of a single PMOS act as a switch and a stack of two NMOS act as a resistors as shown in figure4 (a). In figure 4 (b) shown the lower SVL circuit, which is constructed by using of a single NMOS transistor and multiple PMOS act as a resistors connected in series. The combine circuits of both SVL circuits are also shown in figure 4(c) [13] [14].

      Fig. 4. SVL Circuits

   2. Power gating technique

   Power gating requires, for each circuit that can be turned off, the presence of a header (or footer) sleep transistor that can set the supply voltage of the circuit to ground level (or VDD level for footer) throughout idle times. Power gating also requires control logic to predict when would be a good time to power gate the circuit [15].This technique uses high threshold voltage sleep transistor that cut-off a circuit block when the block is not switching [16]. Here the sleep transistor is connected between actual ground rail and virtual ground [17], [18]. This insertion of sleep transistor divides the power network into a permanent power network connected to the power supply and a virtual power network that drives the cells and can be turned off during inactive period.

   The figure 5 shown the power gating technique are applied on inverter circuit. In this circuit, the supply voltage is turned off during the standby mode by using a PMOS transistor or an NMOS transistor; with proper switch sizing leakage- power can be reduced by more than two orders of magnitude. In active mode, the sleep transistor is on and the circuit functions as usual. In standby mode, the switch transistor is turned off, which disconnects the logic gate from power or ground. The basic mechanism by which the switch transistor reduces the leakage current of the power gated logic transistors is the increased body effect.

   VD

   SLEEP

   Table 1show comparison result of delay and average power of designed D Flip-Flop circuits

   DFF Design using	No. Of Transistor count	Delay	Avg. Power
   PASS Transistors logic	12	21.93NS	426.0NW
   Transmission Gate	18	20.51PS	41.55NW
   Gate Diffusion Input (GDI)	18	14.68NS	37.56NW

   DFF Design using	No. Of Transistor count	Delay	Avg. Power
   PASS Transistors logic	12	21.93NS	426.0NW
   Transmission Gate	18	20.51PS	41.55NW
   Gate Diffusion Input (GDI)	18	14.68NS	37.56NW

   Pull-up Network

   INPUT OUTPUT

   Pull-down

   Network

   SLEEP

   GND

   .

   Fig. 5. Power gating technique

4. SIMULATION AND RESULT

   The proposed circuits are simulated on cadence virtuoso tool using specter simulator at 45nm CMOS technology. Figure 4 show input output waveform of the D Flip-Flop circuit. The table 1 gives the comparative results of power and delay of proposed D Flip-Flops circuits with three different design style of CMOS logic. The obtained result of active and leakage power of D flip-Flop circuits with and without using of proposed SVL and power gating techniques are presented in table 2, 3 and 4.

   Fig. 6. Input Output waveform of D Flip-Flop circuit

   Table 2 show Active and Leakage power of Conventional D Flip-Flop Circuits

   Conventional DFF Design using	Active Power	Leakage Power
   PASS Transistors logic	426.0nw	297.1nw
   Transmission Gate	41.55nw	10.1pw
   Gate Diffusion Input (GDI)	40.25nw	13.87pw

   Table 3 show Active and Leakage power of D Flip-Flop combination of both SVL (upper and lower) Technique based Circuits

   DFF DESIGN USING SVL CIRCUIT	ACTIVE POWER	LEAKAGE POWER
   PASS Transistors logic	286.9NW	230.0NW
   Transmission Gate	40.89NW	9.1PW
   Gate Diffusion Input (GDI)	37.56NW	12.80PW

   Table 3 show Active and Leakage power of D Flip-Flop using power gating Technique based Circuits

   DFF Design Using power gating	Active Power	Leakage Power
   PASS Transistors logic	2.65µW	1.567nW
   Transmission Gate	2.237 µW	3.99pw
   Gate Diffusion Input (GDI)	2.053 µW	2.59pw

5. CONCLUSION

In this paper three CMOS implementations of DFFs using pass transistor logic (PTL), transmission gates and GDI based circuits are proposed. The comparison of average power and delay of proposed circuits are shown in this paper. As per simulation result the GDI based circuits are useful for low power applications, because these CMOS design styles exhibit minimum power as compared to other CMOS design style. The leakage power of all the designs decrease when reduction techniques are applied. This paper also gives comparative analysis of leakage power with different CMOS logic style with and without using of leakage reduction technique. As per simulation result the power gating technique is more effective of all design style as compared to SVL technique. All the simulation results are studied and verified on

cadence virtuoso tool at 45nm CMOS technology with 0 .7V.

Acknowledgment

This work was supported by ITM University Gwalior, with collaboration Cadence Design System, Bangalore.

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Bhanupriya Bhargava (F22) was born on 25th June 1990. She has completed his bachelor of Engineering from MITS, Gwalior, India. She joined M Tech VLSI

with ITM Universe, Gwalior, India. Her major field of interest is Low power VLSI design.

Pradeep Kumar Sharma (M24) was born on 28th August 1988. He has completed his Bachelor of Engineering from B.V.M.

College of Technology and Management, Gwalior. He joined M Tech VLSI with ITM Universe Gwalior, India. His major field of interest is Low power VLSI design.

Shyam Akashe (M36) was born on 22nd May 1976. He received his M Tech from ITM, Gwalior in the year 2006. The author is pursuing Ph. D from Thapar University, Patiala, India on the topic Low Power Memory Cell Design. The Authors major fields of study are Low power VLSI design, VLSI signal

processing FPGA design and communication system.

He is working as Associate Professor in Electronics and Instrumentation Engineering Department of institute of Technology and Management, Gwalior, India. His important research publications are; Implementation of technology scaling on leakage reduction technique using cadence tool with 45nm technology, IEEE 2011; High density and low leakage current based 5T SRAM cell using 45nm technology, IEEE 2011; Multi Vt 7T SRAM cell for high speed application at 45nm technology, IEEE 2011.