Critical Load Protection by using DSTATCOM with Stiff Source

Critical Load Protection by using DSTATCOM with Stiff Source

Dr. P. V. V. Rama Rao

Head of The Department, Electrical and Electronics Engineering

Shri Vishnu Engineering College for Women Bhimavaram, India

Ms. K. Sruthi

Mr. P. Devikiran

Asst.Professor

Electrical and Electronics Engineering Shri Vishnu Engineering College for Women

Bhimavaram,India

M.Tech student, Electrical and Electronics Engineering Shri Vishnu Engineering College for Women Bhimavaram, India

AbstractA novel control design algorithm based DSTATCOM control has been proposed in this paper. DSTATCOM cant be used to protect the loads that are connected to the stiff source from voltage disturbances. This algorithm based DSTATCOM operated in voltage control mode. In voltage control mode the voltage regulation will be quite faster, it protects the critical loads and mitigates voltage and current related power quality issues. Thus with these factors, this scheme allows the compensator to tackle quality issues, THD, UPF and voltage regulation. SIMULINK/MATLAB results are presented.

KeywordsVoltage control mode, stiff source, DSTATCOM, Power Quality, voltage regulation, Current control mode, Voltage source Inverter.

1. INTRODUCTION

   Now-a-days the distribution system suffers from both voltage and current related power quality (PQ) problems. They are low power factor, disturbed source current, voltage distortions and harmonics [1], [2]. The custom power devices are used to mitigate these PQ problems. Depending on the mode of operation A DSTATCOM can mitigate the several power quality problems. A DSTATCOM is connected to the system at Point of common coupling (PCC) is used to mitigate both current and voltage related PQ problems [2]-[5]. In current control mode, the compensator injects harmonic and reactive components of load currents to form balanced and sinusoidal source currents and these currents should be in phase with PCC voltages [3]-[5]. While operating in voltage control mode (VCM), the compensator regulates the voltages to reference value to save the load from voltage disturbances as sag and swell. However both advantages cannot be achieved with one device, as both of them are independent of each other.

   A source is termed as stiff or non-stiff is based on the distance between the source and the load. The source is termed as stiff source when the distance between the source and the load is very small and has negligible feeder impedance, and the source is termed as non-stiff source when the distance between the

   Fig (1): Single-phase equivalent circuit of DSTATCOM.

   In current control mode, the compensator cannot compensate for the disturbances caused by voltage. Therefore CCM cannot be used for voltage disturbances, which is a main drawback of this CCM operation [13]. By indirectly regulating the voltage across the external inductor DSTATCOM provides voltage regulation. During normal operation, the control algorithm makes source currents balanced, sinusoidal and in phase with respective source voltages. During voltage disturbances, a constant voltage is maintained at the load terminal

   This paper considers the DSTATCOM to operate in VCM and uses a novel algorithm to obtain variable reference load voltage as a function of the desired source current. This novel algorithm achieves both the advantages of VCM and CCM with only working in one mode of operation. The performance of this scheme is compared with the conventional method. At nominal load operation, UPF is obtained. Fast voltage regulation is obtained during voltage unbalances. The effectiveness of this novel algorithm is validated by simulation results.

2. DESCRIPTION OF THE EQUIVALENT

   CIRCUIT

   The source Vs and the load il are connected through the

   source and the load is long and has higher feeder impedance.

   external inductor

   Lext

   at point of common coupling. is is the

   source current. Through the LC filter VSI (voltage source

   converter) which is represented as uVdc is connected to the load. Where

   Vdc is the voltage maintained across each capacitor And u is the control variable.

   Depending upon the switching state the control variable can be

   +1 or -1

   The currents through the VSI, DSTATCOM AND C fc are

   i fi , i ftandifc and the source and the load voltages are

   v andv respectively.

   1. COMPUTATION OF REFERENCE VOLTAGE MAGNITUDE( V *t ):

      The advantages provided by the CCM operation are:

      Source currents are balanced and Sinusoidal

      Unity power factor at PCC

      Source supplies load average power and VSI losses

      s t Load voltage must be regulated to achieve the above

      There will be no importance of external impedance under normal operation where as under disturbances by the amount of the sag to be mitigated and the rating of the DSTATCOM the value of the external impedance is decided and the source current is

      I VS0 Vt

      advantages during the normal operation.

      Load voltages are balanced and sinusoidal by using DSTATCOM but contains some switching harmonics which gives unwanted reference source currents when directly used. To compute the reference source currents, the +ve sequence components of load voltages are extracted they are:

      s

      P

      P

      Rext

      • jX

        ext

        i *

        vta1

        • P

      For a practical case

      X R

      .when is minimum then

      sa

      1

      lavg

      loss

      ext ext

      the reactive source current is maximum, for this the source

      * vtb1

      current will supply only losses so the will be minimum.

      isb

      Plavg Ploss

      1

      V V

      V V

      Im I s t S

      * v tc1

      Xext

      isc

      1

      Plavg

      Ploss

      The aim is to protect the critical loads during voltage disturbances by improving the DSTATCOM capability to mitigate the sag. To protect the load, the voltage during the voltage sag is 0.9pu is sufficient. Assuming the reactive current is 20A and the sag is 40% then the value of external inductor will be

      Where 1 v tj1 and P is the average load power

      lavg

      lavg

      2

      2

      ja,b,c

      which can be calculated by using the moving average filter(MAF) and Ploss is the total power loss which can be

      calculated by passing the error that is developed by comparing

      Xext

      0.9 0.6 230 3.45

      20

3. CONTROL SCHEME

   the average dc link voltage (Vdc1+Vdc2) and predefined reference value (2Vdcref) through a PI controller.

   Ploss K pdce Kidc edt

   DSTATCOM -compensated circuit diagram is shown in Fig.1.shows the equivalent single phase representation of

   Where K pdc proportional gain

   DSTATCOM in a distribution network. Variable u is either +1

   Kidc

   integral gain

   or -1 depending upon switching state is a switching function. High switching frequency components are eliminated by shunt capacitance C fc .

   Initially, discrete system modeling is carried out to determine discrete voltage control law. With properly chosen VSI parameters the voltage is regulated so the procedure to design the VSI parameters is described. By using complex Fourier transformations and theory of instantaneous symmetrical component, a magnitude of reference voltage is generated which makes the advantages of CCM at nominal load. The controller block diagram is shown in Fig.2.

   e is he error of the PI controller i.e

   e 2Vdcref Vdc1 Vdc 2

   Once the reference currents are drawn from the source then the reference voltages at the load terminal can be derived.

   By applying the kirchhoffs law to fig (1)

   Vs Is Zext Vt

   For the UPF operation, the source voltage and source current will be in phase

   Vs Is Rext jXext Vt

   The load voltage is:

   Vs Is Rext jIs Xext Vt

   V 2 V I R

   2 I X 2

   t s s

   K

   ext

   s ext

   K

   K

   ia

   pa s

   V V I R

   2 I X 2

   t s s

   ext

   s ext

   K K idc

   The value of Vt lies between 0.9pu and 1.1pu based on

   pdc s

   standards and the advantages of CCM operation are achieved.

   Vt is controlled by source current. The load voltage magnitude lies between 0.9pu and 1.1pu during sag and 1.1pu and 1.8pu

   Fig (2) controller circuit

   during swell. For satisfactory operation maximize the DSTATCOM disturbance with standard ability while keeping the load voltage at safe limits i.e.

   Where,

   0

   A

   1

   Cfc

   L

   L

   Vt 0.9 pu when there is a sag

   1

   • Rf

   Vt 1.1pu when there is a swell

   f Lf

   1. Computation of load angle:

      1

      From the block diagram of controller circuit

      Psh is calculated

      0 C

      by using MAF and

      P is calculated by using PI controller.

      B

      fc

      loss

      By comparing shunt power and power loss an error is

      Vdc

      0

      0

      L

      developed which is passed through the PI controller to compute

      x v

      f

      i t z u i t

      K pa Ploss Psh Kia Ploss Psh dt where

      1 t1T

      fc fi ft

      Psh T

      Vtaifta Vtbi ftb Vtci ftc dt

      To compute the state vector

      x(t) with known initial value

      t1

      Power flows from DSTATCOM to load when

      Psh is positive

      x(t0

      ) , the general time domain solution of (1) is given by:

      and power flows from load to DSTATCOM when

      Psh is

      x ( t ) e A ( t t 0 ) x ( t )

      t

      t

      e A ( t T ) Bz ( T ) dT

      t 0

      (2)

      0

      0

      negative. By taking power from source the VSI losses are

      compensated in steady state so Psh will be negative in steady

      The continuous discrete solution is acquired by replacing

      t kT and t (k 1)T as follows:

      state. 0 d

      In steady state the capacitor voltage decreases from reference

      d

      T kT

      d

      d

      value it represents losses in VSI so

      Ploss will be negative in

      x ( k 1) e ATd x ( k ) d

      kT d

      e A ( Td kT d T ) Bz (T ) dT …….( 3 )

      steady state.

      The difference of

      Psh

      and

      Ploss

      be minimized when

      Psh

      and

      where, k represents the sample and

      Td represents the sampling period

      By changing the integration variable, (3) is written as

      Ploss are equal.

      x ( k 1) e

      ATd

      Td

      x ( k ) e A

      0

      Bd z ( k )………. ( 4 )

   2. INSTANTANEOUS REFERENCE VOLTAGE:

   (4)is rewritten as:

   The three phase reference voltages are taken by selecting the

   x ( k

   1 ) Gx

   ( k ) Hz

   ( k )…….( 5 )

   t

   t

   suitable reference load voltage magnitude and computing load angle

   G and H are sampled matrices of sampling time Td .Matrices

   G and H are calculated for small sampling time as follows:

   Vtrefa

   2V * sint

   G11

   G12

   Vtrefb

   2Vt

   *

   *

   *

   sint 2

   3

   2

   G G21

   G22

   2 2

   Vtrefc

   2Vt

   sint

   3

   G e ATd

   I

   ATd

   A Td ……( 6 )

   2

   Where is the system frequency

   D.GENERATION OF SWITCHING PULSES:

   H H11

   H21

   H21

   H12 H22.

   Td Td

   The state-space representations of the single- phase equivalent circuit shown in Fig 1 are given by:

   H e A Bd

   0

   ( I A ) Bd …..( 7 )

   0

   T 2 T

   T 2 R

   . From (6) and (7), G11 1 d G

   d d f

   12

   12

   x Ax Bz……………….(1)

   T 2V

   2Lf Cfc

   Cfc

   2Lf Cfc

   T

   H11 , d dc

   2Lf Cfc

   , 12 d

   H

   H

   C

   fc

   Hence the capacitor voltage from (5) is given as:

   v fc ( k 1) G 11 v fc ( k ) G 12 i fi ( k ) H 11 u ( k ) H 12 i ft ( k )..( 8 )

   From the equation (8), the terminal voltage should be maintained at reference value and it depends upon the inverter parametersVdc , C fc , R f , L f and Td

   t

   t

   Therefore, inverter parameters must be chosen very carefully. Let v* be the reference load terminal voltage.

   t

   t

   A minimization of cost function is chosen as follows:

   fc

   fc

   J v

   ( k 1) v * ( k 1) 2 …( 9 )

   Fig (3) load current waveforms of phase-a before, during and after load change

   The minimum value of cost function is acquired by differentiating with respect to u(k) . The voltage control-law, from (8) and (10), is given as:

   The source voltage and current waveforms are in phase with each other after the load change

   v fc

   ( k 1) v * ( k 1)….( 10 )

   t

   t

   t

   t

   t

   t

   11

   11

   In (11) V *(k 1) is the unknown future reference voltage. Using a second-order

   u * ( k )

   v * ( k 1) G v

   fc ( k ) G 12 i fi

   ( k ) H

   12 i ft

   ( k )

   (11 )

   Then

   u*(k )

   is convertedH i11nto the ON/OFF switching

   command to corresponding VSI switches using hysteresis controller.

4. SIMULATION RESULTS

   By using the proposed control algorithm and multifunctional DSTATCOM which makes the 3- source currents balanced

   and sinusoidal. To protect the sensitive loads during voltage disturbances, a fast voltage regulation is provided at the load terminal.

   System quantities	values
   Stiff source Vs	230v
   Filter inductance Lf	20mH
   Filter capacitance Cf	10 F
   External inductance Lext	11mH
   Vdc	600v
   Cdc	3000 F

   In the initial, a unbalanced linear and non-linear load of 6.9kw is connected. At t=0.2sec, the load current in phase-a increases by increasing the load to 9.6kw which is shown below figure

   Fig (4) source voltage and current waveforms of phase-a before, during and after load change

   At t=0.8sec a sag is created by reducing the source voltage by 30% to show the voltage regulation capability of DSTATCOM. During this sag period the source current increases.

   Fig (5) source voltage and current waveforms of phase-a before, during and after sag

   Maintaining the voltage of 0.9pu, a fast voltage regulation is provided at the load terminals

   Fig (6) load voltage waveforms of phase-a before, during and after sag

   During normal operation, load change and voltage disturbances a controller regulates the load angle. Voltage at DC bus is regulated around 1200 during the whole process.

   Fig (7) a)load angle b)voltage across dc bus

5. CONCLUSION

Through this paper a new algoritm is used to generate reference voltage for DSTATCOM in voltage control mode. It meets the objectives protecting the load from voltage disturbances under stiff source, fast load voltage regulation, advantages of the ccm operation are achieved while operating in vcm, attaining unity power factor (UPF), harmonics reduction, nearly UPF is attained during load change, losses are decreased so as saving the rating of VSI. Thus, by considering the above one can say PQ is improved. The simulation results have been presented.

REFERENCES

1. Chandan kumar, and Mahesh K. Mishra A Multifunctional DSTATCOM operating under stiff source

2. Chandan Kumar, and Mahesh K. Mishra A Voltage-Controlled DSTATCOM for Power-Quality Improvement.

3. H. Fujita and H. Akagi, Voltage-regulation performance of a shunt active filter intended for installation on a power distribution system, IEEE Trans. Power Electron., vol. 22, no. 3, pp. 10461053, May 2007.

4. Elnady and M. Salama, Unified approach for mitigating voltage sag and voltage flicker using the DSTATCOM, IEEE Trans. PowerDel., vol. 20, no. 2, pt. 1, pp. 9921000, Apr. 2005

5. A. Ghosh and G. Ledwich, Load compensating DSTATCOM in weak ac systems, IEEE Trans. Power Del., vol. 18, no. 4, pp. 13021309,Oct. 2003. ]

6. S. Rahmani, A. Hamadi, and K. Al-Haddad, A Lyapunov-function based control for a three-phase shunt hybrid active filter, IEEE Trans.Ind. Electron., vol. 59, no. 3, pp. 14181429, Mar. 2012.

7. M. K. Mishra and K. Karthikeyan, A fast-acting dc-link voltage controller for three-phase DSTATCOM to compensate ac and dc loads, IEEE Trans. Power Del., vol. 24, no. 4, pp. 22912299, Oct. 2009.

8. M. K. Mishra, A. Ghosh, A. Joshi, and H. M. Suryawanshi, A novel method of load compensation under unbalanced and distorted voltages, IEEE Trans. Power Del., vol. 22, no. 1, pp. 288295, Jan. 2007.

9. M. K.Mishra, A. Ghosh, and A. Joshi, Operation of a DSTATCOM in voltage control mode, IEEE Trans. Power Del., vol. 18, no. 1, pp. 258 264, Jan. 2003.

10. A. Jain, K. Joshi, A. Behal, and N. Mohan, Voltage regulation with STATCOMs: Modeling, control and results, IEEE Trans. Power Del., vol. 21, no. 2, pp. 726735, Apr. 2006.

11. R. Gupta, A. Ghosh, and A. Joshi, Switching characterization of cascaded multilevel-inverter-controlled systems, IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 10471058, Mar. 2008.

12. P. Mitra and G.Venayagamoorthy, An adaptive control strategy for DSTATCOM applications in an electric ship power system, IEEE Trans. Power Electron., vol. 25, no. 1, pp. 95104, Jan. 2010.