Cross layer Optimization of Optical Node in High Speed Network

Cross layer Optimization of Optical Node in High Speed Network

Ankita Agarwal

Lecturer,

Electronics & Telecommunication Department International Institute of Information Technology Pune, India

Dr. Subodh Wairya

Associate Professor,

Electronics & Communication Department, IET Lucknow Lucknow, India

Abstract Optical switching system based on packet switching referred as Optical Packet Switching is considered as next generation high speed data transfer technology. In OPS, the design of an efficient optical node is a complex problem. Performance evaluation of the switches (Optical nodes) is done both at physical as well as network layer. Parameter like packet loss probability is used to measure performance of the switch in network layer. For efficient switching high throughput is desired therefore low packet loss probability is to be achieved. In the physical layer, effects of system impairments on bit-error rate (BER) are studied. Physical layer impairments are dominated by amplified spontaneous emission (ASE) noise and crosstalk, which also leads to packet drop. In this paper, cross-layer optimization of an AWG based optical packets switch is done. The detailed analysis shows that the architecture presented here can be operated in the sub-micro watts with very good quality of service in terms of packet loss rate (PLR).

KeywordsBER; OPS; PLR; ASE; Optical Node

1. INTRODUCTION

   OPS is a transmission technology which utilizes the huge transmission bandwidth of optical fiber very efficiently using WDM technology. In OPS, data is transmitted in forms of packets which are transmitted optically [1]. Each packet is composed of header and payload. Header is processed electronically after O/E conversion at each node while payload remains in optical domain [2]. As header is processed at each intermediate node, it is send at lower data rates. Header contains meaningful information like: source address, destination address etc.

   Currently, in optical transport networks, first light-path paths are set, then data travels over it[1-4]. These all-optical switches are transparent to information carried over the light path. At the same time, optical circuit switching technology has made it feasible to have virtual topologies over an actual physical fiber topology (layout). It allows us to rapidly deliver the enormous bandwidth of WDM networks to customer, while remaining inefficient at the physical layer. One requires packet for efficient use of the physical layer. The possibility of packet switching using photonic technologies allows all-optical packet switched networks where packets remain in optical form without undergoing optoelectronic conversion at intermediate nodes [5-8]. The design of the OPS network is shown in Fig. 1.

   Fig. 1. Optical Packet Switching Netwrok Full layout

   The all-optical packet switches placed in the core network as shown in figure 2, processes the packets and converts the header of the packet to electrical form and maintains the payload in optical form. The header information is used for routing of the packet. Once the packet reaches the egress node, the aggregated optical packets can be separated optically (if required) and directed towards the client network. We can call them as aggregate core transport networks.

2. SWITCH DESIGN AND POWER BUDGET ANALYSIS

   The design of optical node is shown in Fig. 2. Switch size is assumed to be NxN, with m buffer modules [9]. Here, TWC placed at the input of the switch plays major role as it tunes the wavelength of the incoming packets such that either they can be placed in any buffer (1,,m) depending on the required amount of delay, or can be send to the output of the scheduling AWG, from here packets can be transferred to actual output by tuning their wavelengths using the TWC placed at the input of the switching AWG. The detailed description and advantages of the architecture can be found in [9-10].The switch design very efficiently uses the wavelength domain routing pattern of the AWG. In the paper design proposed in [9] is modified by placing SOA just after scheduling AWG so that the loss of both buffered as well as direct packets can be compensated.

   C. Noise Analysis

   s sp-sp sig-sp s-sp th

   The information in optical domain suffers from various noise sources. These noises terms beat with each other to produce shot noise, ASE-ASE beat noise, sig-ASE beat noise, shot- ASE beat noise and thermal noise variances are denoted by 2 , 2 , 2 , 2 , and 2 respectively [11]. Various noise components are defined as

   Shot noise

   s e

   2 2qRPB

   ASE-ASE beat noise

   (7)

   2 2R2 P (2B B ) Be

   (8)

   B

   spsp sp o e 2

   0

   R P

   Sig-ASE beat noise

   Fig. 2. WDM based AWG Optical Router

   1. Loss Analysis

      2

      sig sp

      4 2 Psp Be B0

      (9)

      The loss of input unit is

      Shot-ASE beat noise

      Ain LTWC

      (1)

      2 2qRP B

      (10)

      The loss of buffer is

      ssp sp e

      Thermal noise

      A L2 N2 N L

      (2)

      b AWG FDL

      2 4KBTBe th R

      (11)

      Here,

      2 N2 N

      L

      AWG

      is loss due to scheduling AWG.

      LFDL is the

      L

      loss due to the fiber delay lines.

      L

      Similarly the loss of output unit is

      The expression for P and Psp will be given by

      P bPin ,

      A L2 N2 N L LNN

      (3)

      P n

      (G 1)h B

      Aout

      (12)

      out AWG TWC AWG

      By combing all the above losses, total loss of the switch is

      sp sp

      3 0 2 N2 N AWG

      AT Ain Ab Aout

      (4)

      The total noise variance for bit b is

      2 b 2 2 2 2

      2

      (13)

      To fully compensate the loss, the gain of the SOA placed at

      s spsp

      sp sig

      s sp th

      the input of the switching AWG must

      satisfy Ain Ab AoutG 1.

      I 1 I 0 RP 1 RP 0

      BER Q 1 0 Q 1 0

      (14)

   2. Power Analysis

   1 z2

   Qz e 2 dz

   (15)

   In the sub-section power analysis is presented. Power entering the switch for bit b is

   2 z

   Ps bPin b [0,1]

   The extinction ratio ( = P0/P1) is assumed to be zero. Power at the output of the switch is

   (5)

   The equation 14 will provide the BER at different power

   L

   levels, which is an important parameter in physical layer analysis. In the next subsection- network layer parameter packet loss probability will be obtained using the computer simulation.

   P P n

   (G 1)h B

   Aout

   . (6)

   out in sp

   3 0 2 N2 N AWG

   TABLE I. LIST OF PARAMETRES USED IN CALCULATION

   Symbol	Parameter	Value
   N	Size of the switch	16
   nsp	Population inversion factor	1.2
   c	Speed of light	3108 m / s
   N	Refractive index of fiber	1.55
   R	Responsively	1.28 A/W
   e	Electronic charge	1.61019 C
   Be	Electrical bandwidth	20GHz
   B0	Optical bandwidth	40GHz
   LTWC	TWC insertion loss	2.0 dB
   L2 N2 N AWG LN N AWG	Loss of Scheduling and Switching AWG (32 channels)	3.0 dB
   LFDL	Loss of the fiber loop	0.2 dB/km

   1. Simulation Analysis

      The simulation is done in MATLAB. In the simulation, for traffic generation and destination assignment random traffic model is considered..In the random traffic model, it is assumed:

      1. Packet can arrive to any of the input of switch with equal probability p.

      2. Each packet has equal probability (1/N) to go to any of the output, where N is the number of output of the switch.

   The probability of arrival of that K packets for a particular tagged output is given by

   1. Power Budget Analysis Results

      TABLE II. BER ANALYSIS AT VARIOUS POWER LEVELS FOR SWITCH SIZE N=16, BUFFER=16 AND PACKET SIZE OF 1000 BITS

      Power W	BER
      	Br=10 Gbps	Br=20 Gbps	Br=40 Gbps
      0.6	9.6175X 10-4	9.2421X 10-4	9.0591X 10-4
      1	1.7166X 10-5	1.6066X 10-5	1.5540X 10-5
      2	8.4966X 10-10	7.4348X 10-10	6.9524X 10-10
      3	4.4044X 10-14	3.6002 X 10-14	3.2534 X 10-14
      4	2.2980X 10-18	1.7540 X 10-18	1.5314 X 10-18
      5	1.1969X 10-22	8.5287 X 10-23	7.1930 X 10-23
      6	6.2099X 10-27	4.1298 X 10-27	3.3643 X 10-27
      7	3.2074X 10-31	1.9906 X 10-31	1.5662 X 10-31
      8	1.6493 X 10-36	9.5510 X 10-36	7.2579 X 10-36
      9	8.4454 X 10-40	4.5630 X 10-40	3.3487 X 10-40
      10	4.3076 X 10-44	2.1713 X 10-44	1.5388 X 10-44

      In above table II results are tabulated for buffer size 16 and for different lengths of packets or time slots. Bit rate 10 Gbps, 20 Gbps, 40 Gbps correspond to length of 19.3 m, 9.67 m, 4.83 m respectively. Considering loss of fiber to be 0.2 dB/Km, the amount of loss will be very less. Hence, with above table II, it can be concluded that power level of 2µW will be sufficient for the proper operation of the switch (BER10-9). Considering power of 2µW if the data rate is increased from 10 Gbps to 20 Gbps and 40 Gbps there is reduction in BER. Thus as slot length decreases BER improves.

      TABLE III. BER ANALYSIS AT VARIOUS POWER LEVELS FOR SWITCH SIZE N=16, BUFFER=16 AND PACKET SIZE OF 10000 BITS

      P[K ] NC

      p K

      K N 1

      p N K

      N

      Power W	BER
      	Br=10 Gbps	Br=20 Gbps	Br=40 Gbps
      0.6	0.0019	0.0013	0.0011
      1	5.2698X 10-5	2.8719X 10-5	2.0885 X 10-5
      2	8.1129X 10-9	2.3953X 10-9	1.2614X 10-9
      3	1.3260X 10-12	2.1056X 10-13	7.9986X 10-14
      4	2.1970X 10-16	1.8691X 10-17	5.1113X 10-18
      5	3.6505 10-20	1.6598X 10-21	3.2633X 10-22
      6	6.0613X 10-24	1.4703X 10-25	2.0764X 10-26
      7	1.0044X 10-27	1.2982X 10-29	1.3159X 10-30
      8	1.6602 X 10-31	1.1421 X 10-33	8.3053 X 10-35
      9	2.7370X 10-35	1.0013 X 10-37	5.2213X 10-39
      10	4.5005 X 10-39	8.7502 X 10-42	3.2704 X 10-43

      (16)

      It must be remembered that module m provides a delay of m

      slots.

3. RESULTS AND CROSS LAYER OPTIMIZATION

   In table III results are again reproduced using packet size of 10000 bits rest of parameters are same as in Table II. The increase in the number of bits, leads to an increase in slot In

   In this section physical layer results are presented. The length of the fiber loop is taken equal to the packet duration equivalent of slot duration and is given by

   L = cb / nBr (17)

   Here, c (=3×108 m/s) is the speed of light, b is the total number of bits stored in fiber delay lines, n (=1.55) is the refractive index and Br is the bit rate.

   In table III results are again reproduced using packet size of 10000 bits rest of parameters are same as in table II. The slot length is increased due to increase in the number of bits and correspondingly buffer length increases, thus more power is required to maintain BER 10-9. In above table the results are plotted for Bit rate 10 Gbps, 20 Gbps, 40 Gbps correspond to length of fiber as 193 m, 96.7 m, 48.3 m respectively and again a power level of 3µW will be required for the switch to operate properly. Thus increasing slot length by a factor of 10 the power required to achieve acceptable signal quality increases by 1 µW.

   1. Simulation Results

      In this section, network layer results in terms of packet loss probability are presented. Simulation is done on MATLAB and to obtain steady state results simulation is repeated for 106 runs.

      100

      Loss Probability

      10-2

      10-4

      N=16, B=2

      In figure 4 plots are obtained for various cases of scaled switch architecture with N=B. If total number of inputs of scheduling AWG is 2N= 32 then for the case of N=B half of the ports used as input and rest half as buffer. Considering the case of N=B=4 and N=B=16, even at the load of 0.8, the packet loss improvement is more than 100. Thus it is evident from figure that as switch size and buffer is increased while keeping their ratio constant, packet loss probability decreases.

   2. Cross Layer Optimization

   The schema of cross layer optimization is shown below in figure 5; here it is shown that for desired packet loss, how switch buffer and power will be fixed for a particular switch size.

   10-6

   10-8

   N=16, B=4 N=16, B=8 N=16, B=16

   0.2 0.4 0.6 0.8 1

   Load on the system

   Fig. 3: Packet loss probability vs. load (Random Traffic) with varying number of buffer module

   In figure 3, switch of size N = 16 and buffer is varying from 2 to 16 is considered. It is clear from the figure that if no of inputs are 16 then to achieve very low packet loss probability of order 10-4 at higher load (0.6) buffer modules required are at least 8 or above. If number of modules are decreased to 4 or 2 packets loss increases. At load of 0.6 with B=4, loss probability is approximately 10-3. If traffic load on switch is further increased to 0.8 then required buffer size is at least 16 to achieve low packet loss. The switch performs well in terms of the packet loss probability as we are able to achieve low packet loss probability. It is also observable form the figure as the number of buffer modules increases, the packet loss probability also improves.

   2N=8, B=4

   2N=16, B=8

   2N=32, B=16

   10-1

   Lss Probability

   10-2

   10-3

   10-4

   0.2 0.4 0.6 0.8 1

   Load on the system

   Fig. 5: Flow diagram for Cross layer optimization

   Let for a particular application the desired packet loss for switch of size N=16 is 10-4 at the load of 0.8. First of all consider figure 4, where packet loss for N=16 for different buffer space is shown. Thus as per the requirement the minimum buffer to be considered is 16. Now we have fixed our design parameters for the switch which are N=16 and B=16. Referring Table II, the desired power would be 2µW. The length of the packet will of 1000 bits and maximum data transmission speed is 40 Gbps. Similarly if packet of 10,000 is to be used than required power is 3µW.

4. CONCLUSIONS

This paper presents the cross layer optimization of an AWG based switch. The cross layer optimization is performed between the physical and network layers. This analysis is very important when switches are cascaded or placed in the network. It is shown that to get desired quality of service, a particular switch design is needed with some minimum amount of power. In general switch size is fixed thus this analysis fix the buffer size, packet size at different bit rates and required amount of power for the correct reception of the signal at the output.

Fig. 4: Packet loss probability vs. load (Random Traffic) for N=B

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