Design and Control of Interline Unified Power Quality Conditioner for Power Quality Disturbances

Design and Control of Interline Unified Power Quality Conditioner for Power Quality Disturbances

B.Sasikala1, Khamruddin Syed2

Department of Electrical and Electronics, K. G. Reddy College of Engineering and Technology

Abstract

Proliferation of electronic equipment in commercial and industrial processes has resulted in increasingly sensitive electrical loads to be fed from power distribution system which introduce contamination to voltage and current waveforms at the point of common coupling (PCC) of industrial loads.This paper proposes a new connection for a UPQC to improve the Power Quality (PQ) of two feeders in a distribution system. Interline Unified Power Quality Conditioner (IUPQC), specifically aims at the integration of series VSC and Shunt VSC to provide high quality power supply by means of voltage sag compensation, harmonic elimination and power factor correction in a power distribution network, so that improved PQ can be made available at the point of common coupling . The structure, control and capability of the IUPQC are discussed in this paper. The efficiency of the proposed configuration has been verified through simulation using MATLAB/SIMULINK.

1. Introduction

   PQ problems have received a great attention nowadays because of their ill effects. Nowadays most of the domestic and industrial equipment are corrupting the quality of the delivered power. The most common PQ problem is due to the utilization of modern semiconductor switching devices more and more in a wide range of applications in distribution networks , particularly in domestic and industrial loads These semiconductor devices present nonlinear operational characteristics, which introduce contamination to voltage and current waveforms at PCC of industrial loads. Nowadays VSC based custom power devices are increasingly being used in custom power applications for improving the PQ of power distribution systems. Devices such as Distribution Static Compensator (DSTATCOM) and Dynamic Voltage Restorer (DVR) have already been in use. A

   DSTATCOM can compensate for distortion and unbalance in a load. A DVR an compensate for voltage sag/swell and distortion in the supply side voltage such that the voltage across a sensitive/critical load terminal is perfectly regulated. A UPQC can perform the functions of both DSTATCOM and DVR. The UPQC consists of two VSCs that are connected to a common DC bus. One of the VSCs is connected in series with a distribution feeder, while the other one is connected in shunt with the same feeder. The DC links of both VSCs are supplied through a common DC capacitor.

   This paper presents the new connection for UPQC i.e., IUPQC which is the most sophisticated mitigating device for the PQ problems. It was firstly introduced to mitigate the current harmonics and voltage disturbances. The main aim of the IUPQC is to hold the voltages Vt1 and Vl2 constant against voltage sag/sell/any power disturbances in either of the feeders. Many contributions were introduced to modify the configurations and the control algorithms to enhance its performance. Most of the existing control algorithms which are employed to control IUPQC have some drawbacks. These drawbacks have significant influence on the performance of IUPQC.

2. IUPQC Connection

   The single-line diagram of an IUPQC connected distribution system is shown in Fig. 1.

   Two feeders, Feeder-1 and Feeder-2, which are connected to two different substations, supply the system loads L-1 and L-2. The supply voltages are denoted by Vs1 and Vs2. It is assumed that the IUPQC is connected to two buses B-1 and B-2, the voltages of which are denoted by Vt1 and Vt2, respectively. Further two feeder currents are denoted by is1 and is2 while the load currents are denoted by il1 and il2. The load L-2 voltage is denoted by Vl2. The purpose of the IUPQC is to hold the voltages Vt1 and Vl2 constant against voltage sag/swell, temporary interruption and momentary interruption etc. in either of

   the two feeders. It has been demonstrated that the IUPQC can absorb power from one feeder (say Feeder-1) to hold Vl2 constant in case of a sag in the voltage Vs1. This can be accomplished as the two VSCs are supplied by a common dc capacitor. The dc capacitor voltage control has been discussed here along with voltage reference generation strategy. Also, the limits of achievable performance have been computed. The performance of the IUPQC has been evaluated through simulation studies using MATLAB/SIMULINK.

   Fig. 1. Single-line diagram of an IUPQC distribution system

   But basically IUPQC is nothing but the device UPQC kept in between two individual feeders, (called feeder-1 and feeder-2). UPQC consists of two back to back connected IGBT based voltage source bi-directional converters or VSCs (called VSC-1 and VSC-2) with a common DC bus. VSC-1 is connected in shunt with feeder-1 while VSC-2 is placed in series with the feeder-

   2. All the inverters are supplied from a common single DC capacitor and each inverter has a transformer connected at its output. The AC filter capacitors are also connected in each phase (Fig.1) to prevent the flow of the harmonic currents generated due to switching. The six inverters of the IUPQC are controlled independent.

   Fig. 2. Typical IUPQC connected in a distribution system.

   An IUPQC connected to a distribution system is shown in Fig. 2, the feeder impedances are denoted by the pairs (Rs1, Ls1) and (Rs2, Ls2). It can be seen that the two feeders supply the loads L-1 and L-2. The load L-1 is assumed to have two separate components an unbalanced part (L-11) and a non-linear part (L-12). The currents drawn by these two loads are denoted by il11 and il12, respectively. We further assume that the load L-2 is a sensitive load that requires uninterrupted and regulated voltage. The system parameters are mentioned in Table1.

   Table 1: System parameters

   System quantities	Values
   System fundamental frequency	50Hz
   Voltage source Vs1	11kv(L-L,rms), phase angle 00
   Voltage source Vs2	11kv(L-L,rms), phase angle 00
   Feeder-1 (Rs1 + j2fLs1)	Impedance:3.05+j0.036
   Feeder-2 (Rs1 + j2fLs2)	Impedance:3.05+j30.73
   Load L-11 Unbalanced RL component	Phase a: 24.2+j62.54 Phase b: 36.1+j81.86 Phase b: 48.2+j97.90
   Load L-12 Non-linear component	A three-phase diode rectifier That Supplies a load of 250+j31.41
   Balanced load L-2 Impedance	95+j85.86

3. Design Considerations

The design considerations of IUPQC can be evaluated by using the following filtering systems

1. Active Filtering System

   The active filtering system is based on a philosophy that addresses the load current distortion from a time domain rather than a frequency domain approach. The most effective way to import the distortive power factor in a non-sinusoidal situation is to use a nonlinear active device that directly compensates for the load current distortion. The performance of these active filters is based on three basic design criteria. They are:

   1. The design of the power inverter (semiconductor switches, inductances, capacitors, dc voltage).

   2. The PWM control method (hysterisis, triangular carrier, periodical sampling)

   li>

   Method used to obtain the current reference or the control strategy used to generate the reference template.

2. Design of Power Inverters

Inverter: Both series voltage control and shunt current control involve use of voltage source converters. Both these inverters each consisting of six IGBTs with a parallel diode connected in reverse with each IGBT are operated in current control mode employing PWM control technique

Capacitor: Capacitor is used as an interface between the two back to back connected inverters and the voltage across it acts as the dc voltage source driving the inverters. The IUPQC parameters are shown in Table2.

Table 2: IUPQC Parameters

1. Control Strategy for IUPQC

1. Shunt Control Strategy

   Shunt control strategy shown in Fig. 3 involves not only generating reference current to compensate the harmonic currents but also charging the capacitor to the required value to drive the inverters.

   Fig. 3. Block diagram for generation of gating signals

   PI Control

   With a view to have a self regulated dc bus, the voltage across the capacitor is sensed at regular intervals and controlled by employing a suitable closed loop control. The DC link voltage, Vdc is sensed at a regular interval and is compared with its reference counterpart Vdc *. The error signal is processed in a PI controller. The output of the PI controller is denoted as isp(n). A limit is put on the output of controller this ensures that the source supplies active power of the load and dc bus of the UPQC. Later part of active power supplied by source is used to provide a self supported DC link of the UPQC. Thus, the DC bus voltage of the UPQC is maintained to have a proper current control. Three phase reference supply currents (isa*, isb*, isc*). Subtraction of load currents (ila, ilb and ilc) from the reference supply currents (ila*, ilb*, ilc*) results in three phase reference currents (isha*, ishb*, ishc*) for the shunt inverter.

   These reference currents Iref (isha*, ishb*, ishc*) are compared with actual shunt compensating currents Iact (isha, ishb, ishc) and the error signals are then converted into (or processed to give) switching pulses using PWM technique which are further used to drive shunt inverter. In response to the PWM gating signals the shunt inverter supplies harmonic currents required by load. (In addition to this it also supplies the reactive power demand of the load). In effect, the shunt bi-directional converter that is connected through an inductor in parallel with the load terminals accomplishes three functions simultaneously. It injects reactive current to compensate current harmonics of the load. It provides reactive power for the load and thereby improve power factor of the system. It also draws the fundamental current to compensate the power loss of the system and make the voltage of DC capacitor constant. The subsystems of shunt controller and pwm signal generation subsystems are shown in Fig. 4 and Fig. 5.

   Fig. 4. PWM Shunt controller (Subsystem)

   Fig. 5. Direct Shunt controller (Subsystem)

2. Series control strategy

The series controller could be a variable impedance, such as capacitor, reactor etc. Power electronics based variable source of main frequency, sub synchronous and harmonic frequencies to serve the desired need. In principle, all series controllers inject voltage in series with the line. Even variable impedance multiplied by a current flow through it, represents an injected series voltage in the line. The block diagram is shown in Fig. 6.

Fig. 6. Block diagram for generation of gating signals

The series inverter, which is also operated in current control mode, isolates the load from the supply by introducing a voltage source in between. This voltage source compensates supply voltage deviations such as sag and swell. In closed loop control scheme of the series inverter, the three phase load voltage (Vla, Vlb, Vlc) are subtracted from the three phase supply voltage (Vsa, Vsb, Vsc), and are also compared with reference supply voltage which results in three phase reference voltages (Vla*, Vlb*, Vlc*). These reference voltages are to be injected in series with the load. By taking recourse to a suitable transformation, the three phase reference currents (isea*, iseb*, isec*) of the series inverter are obtained from the three phase reference voltages (Vla*, Vlb*, Vlc*). The PWM generation subsystem of series controller shown in Fig. 7.

Fig. 7. PWM Series controller (Subsystem)

isa* = isp.usa; isb* = isp.usb; isc* = isp.usc; (3) To obtain reference currents, three phase load currents are subtracted from three phase reference supply currents:

These reference currents (isea*, iseb*, isec*) are fed

isha

* = isa

• – ila; i

  shb

  * = isb

• – ilb

; (4)

to a PWM current controller along with their sensed counterparts (isea, iseb, isec). The gating signals obtained from PWM current controller ensure that the series inverter meets the demand of voltage sag and swell, thereby providing sinusoidal voltage to load. Thus series inverter plays an important role to increase the reliability of quality of supply voltage at the load, by injecting suitable voltage with the supply, whenever the supply voltage undergoes sag. The series inverter acts as a load to the common DC link between the two inverters. When sag occurs series inverter exhausts the energy of the dc link. Thus, UPQC, unlike Dynamic Voltage Restorer, does not need any external storage device or additional converter (diode bridge rectifier) to supply the DC link voltage.

The direct series controller subsystem as shown in Fig.8

Fig. 8. Direct Series controller (Subsystem)

1. Model Equations of the IUPQC

   1. Computation of Control Quantities of Shunt Inverter

      The amplitude of the supply voltage is computed from the three phase sensed values as:

      vsm =[ 2/3(vsa2 + vsb2 +vsc2)]1/2 (1) The three phase unit current vectors are computed as: usa = vsa/vsm; usb = vsb/vsm; usc = vsc/vsm; (2)

      Multiplication of three phase unit current vectors (usa, usb and usc) with the amplitude of the supply current (isp) results in the three-phase reference supply currents as:

      ishc* = isc* – ilc; (5)

      These are the iref for Direct current control technique of shunt inverter. The iref are compared with iact in PWM current controller to obtain the switching signals for the devices used in the shunt inverter.

   2. Computation of Control Quantities of Series Inverter

   The supply voltage and load voltage are sensed and there from, the desired injected voltage is computed as follows: vinj=vs-vl (6)

   The magnitude of the injected voltage is expressed as: vinj= |vinj| (7)

   Whereas, the phase of injected voltage is given as:

   pq

   pq

   inj= tan(Re[v ]/Im[v ]) (8) for the purpose of compensation of harmonics in load voltage, the following inequalities are followed: vinj<vinjmaxmagnitude control; (9)

   0<inj<3600hase control; (10) Three phase reference values of the injected voltages are expressed as:

   Vla*= (11)

   Vlb*= (12)

   Vlc*= (13)

   The three phase reference currents (iref) of the series inverter are computed as follows:

   isea*= vla*/zse; iseb* = vlb*/zse; isec * = vlc*/zse; (4) The impedance zse includes the impedance of insertion transformer. The currents (isea*, iseb*, isec*) are ideal current to be maintained through the secondary winding of insertion transformer in order to inject voltages (Vla, Vlb, Vlc) thereby accomplishing the desired task of compensation of the voltage sag. The currents iref (isea*, iseb*, isec*) are compared with Iact (isha, ishb, ishc) in PWM current controller, as a result six switching signals are obtained for the IGBTs of the series inverter

2. Operation Of IUPQC for Different Power Distrubances

   Now, the performance of IUPQC has been evaluated considering various disturbance conditions.

   Table. 3: IEEE Standard Power Quality Disturbances

   (c) Load voltage in phase A (d) The DC capacitor voltage

   The Total Harmonic Distortion (THD) at load side is found to be 1.02%. The source voltage THD is effectively found to be 0.045%.

   Compensating Load Current Harmonics Using Direct Current Control Technique

   source current

   200

   0

   The table shows that various IEEE Standard

   -200

   shunt compensating current

   1000

   0

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   Power Quality disturbances, which are being applied to IUPQC and analyzing the performance.

   -1000

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   load voltage

   100

   0

   IUPQC with series and shunt PI Controller:

   -100

   dc link voltage

   5000

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   A 3-phase supply voltage of 11kv line to line, 50Hz with different disturbances at source end, non-linear and unbalanced load at load end is considered. Non-linear load (whether Diode Rectifier feeding an RL load or thyristor feeding an RL load) injects current harmonics into the system. IUPQC is able to reduce the harmonics from entering into the system using shunt control.

   Case 1: Impulsive

   1. Iupqc-Mitigating The Effect Of Impulsive Sag

      A 3-phase supply voltage (11kv, 50Hz) with impulsive sag of 0.3 pu magnitude and the duration about

      0.5 to 30 cycles is taken. With the system operating in the steady state, a 30 cycle impulsive voltage sag of 0.3 pu magnitude is occurring at 0.2 msec for which the peak of the supply voltage reduces from its nominal value of 11kv to 8kv.

      4

      x 10

      0

      0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

      Fig. 2: Simulation results-mitigating the effect of impulsive sag of 0.3 pu with duration 0.5 to 30 cycles using direct current control technique with PI controller

      (a) Load current in phase A (b)shunt compensating current in phase A

      (c)Supply current in phase-A (d) DC capacitor voltage The Total Harmonic Distortion (THD) at load

      side is found to be 0.294%. The source current THD was effectively found to be 14.30%.

   2. Iupqc-Mitigating The Effect Of Impulsive Swell

   A 3-phase supply voltage (11kv, 50Hz) with impulsive swell of 0.3 pu magnitude and the duration about 0.5 to 30 cycles is taken. With the system operating in the steady state, a 0.5 to 30 cycle impulsive voltage swell of 0.3 pu magnitude is occurring at 0.2 msec for which the peak of the supply voltage raises from its nominal value of 11kv to 14kv.

   source voltage

   1

   0

   -1

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   4

   4

   x 10

   series

   load compensating source

   voltage voltage voltage

   2

   series compensating voltage

   x 10

   1

   0

   -1

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   4

   x 10

   load voltage

   1

   0

   -1

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   dc link voltage

   5000

   0

   0

   -2

   1

   0

   -1

   1

   0

   -1

   dc link voltage

   10000

   5000

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   4

   x 10

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   4

   x 10

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   time

   0

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   time

   Fig. 1: Simulation results mitigating the effect of impulsive sag of 0.3 pu with duration 0.5 to 30 cycles using series voltage controller.

   1. Supply voltage in phase-A (b) Series injected voltage in phase-A

   Fig. 3: Simulation results mitigating the effect of impulsive swell of 0.3 pu with duration 0.5 to 30 cycles using series voltage controller.

   (a) Supply voltage in phase-A (b) Series injected voltage in phase-A

   (c) Load voltage in phase A (d) The DC capacitor voltage

   The Total Harmonic Distortion (THD) at load side is found to be 1.71%. The source voltage THD is effectively found to be 0.045%.

   Compensating Load Current Harmonics Using Direct Current Control Technique

   source current

   200

   0

   -200

   shunt compensating current

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   2000

   0

   -2000

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   load voltage

   100

   0

   -100

   Fig. 5: Simulation results mitigating the effect of momentary sag of 0.2 pu with duration 20 to 30 cycles using series voltage controller.

   (a) Supply voltage in phase-A (b) Series injected voltage in phase-A

   (c) Load voltage in phase A (d) The DC capacitor voltage

   Fig. 5(a) shows the series injected voltage, injecting the required compensating voltage. Fig. 5(b) shows the compensated feeder-2 load voltage. As can be seen from the Fig. 5(c) there is perfect compensation for momentary sag. Fig. 5(d) shows the DC link voltage. In order to supply the balanced power required to the load, the DC capacitor voltage drops as soon as the sag occurs. As the sag is removed the capacitor voltage returns to the steady

   dc link voltage

   10000

   5000

   0

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   state.

   The Total Harmonic Distortion (THD) at load

   0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

   time

   Fig. 4: Simulation results- mitigating the effect of impulsive swell of 0.3 pu with duration 0.5 to 30 cycles using direct current control technique with PI cotroller.

   (a) Load current in phase A (b) shunt compensating current in phase A

   (c)Supply current in phase-A (d) DC capacitor voltage The Total Harmonic Distortion (THD) at load

   side is found to be 0.584%. The source current THD was effectively found to be 14.61%.

   side is found to be 1.65%. The source voltage THD is effectively found to be 0.045%.

   Compensating Load Current Harmonics Using Direct Current Control Technique

   source current

   200

   0

   -200

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

   shunt

   compensating current

   1000

   Case 2: Momentary

   1. Iupqc-Mitigating The Effect Of Momentary Sag

      A 3-phase supply voltage (11kv, 50Hz) with momentary sag of 0.2 pu magnitude with the duration about 20 to 30 cycles is taken. With the system operating in the steady state, a 20-30 cycle momentary sag of 0.2 pu magnitude is occurring at 8 msec for which the peak of

      0

      -1000

      load current

      100

      0

      -100

      dc link voltage

      10000

      5000

      0

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      time

      the supply reduces from its nominal value of 11kv to 9kv.

      4

      x 10

      source voltage

      1

      0

      -1

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      4

      series

      compensating voltage

      x 10

      1

      0

      -1

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      4

      x 10

      Fig. 6: Simulation results- mitigating the effect of momentary sag of 0.2 pu with duration 20 to 30 cycles using direct current control technique with PI controller.

      (a) Load current in phase A (b) shunt compensating current in phase A

      (c)Supply current in phase-A (d) DC capacitor voltage The Total Harmonic Distortion (THD) at load

      side is found to be 0.496%. The source current THD was effectively found to be 14.44%.

      load voltage

      1

      0

      -1

      dc link voltage

      10000

      5000

      0

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      time

   2. Iupqc-Mitigating The Effect Of Momentary Swell

   A 3-phase supply voltage (11kv, 50Hz) with momentary swell of 0.3 pu magnitude with the duration about 20 to 30 cycles is taken. With the system operating in the steady state, a 20-30 cycle momentary swell of 0.3 pu magnitude is occurring at 8 msec for which the peak of the supply raises from its nominal value of 11kv to 8kv.

   4

   x 10

   source voltage

   2

   0

   -2

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

   4

   series

   compensating voltage

   x 10

   1

   0

   -1

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

   4

   x 10

   load voltage

   1

   0

   -1

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

   dc link voltage

   10000

   5000

   0

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

   time

   Fig. 7: Simulation results mitigating the effect of momentary swell of 0.3 pu with duration 20 to 30 cycles using series voltage controller.

   (a) Supply voltage in phase-A (b) Series injected voltage in phase-A

   (c) Load voltage in phase A (d) The DC capacitor voltage

   Fig. 8:Simulation results- mitigating the effect of momentary swell of 0.3 pu with duration 20 to 30 cycles using direct current control technique with PI controller.

   (a) Load current in phase A (b) shunt compensating current in phase A

   (c)Supply current in phase-A (d) DC capacitor voltage The Total Harmonic Distortion (THD) at load

   side is found to be 0.567%. The source current THD was effectively found to be 14.60%.

   CASE 3: TEMPORARY

   1. Iupqc-Mitigating The Effect Of Temporary Sag

      A 3-phase supply voltage (11kv, 50Hz) with temporary sag of 0.07 pu magnitude with the duration about 30 to 40 cycles is taken. With the system operating in the steady state, a 30-40 cycle momentary sag of 0.07 pu magnitude is occurring at 12 msec for which the peak of thesupply reduces from its nominal value of 11kv to 9kv.

      4

      source voltage

      x 10

      Fig. 7(a) shows the series injected voltage, injecting the required compensating voltage. Fig. 7(b) shows the compensated feeder-2 load voltage. As can be seen from the Fig. 7(c) there is perfect compensation for momentary swell. Fig. 7(d) shows the DC link voltage. In order to supply the balanced power required to the load, the DC capacitor voltage raises as soon as the sag occurs. As the swell is removed the capacitor voltage returns to the

      1

      0

      -1

      0

      4

      series

      compensating voltage

      x 10

      1

      0

      -1

      0

      4

      x 10

      load voltage

      1

      0

      -1

      0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      steady state.

      The Total Harmonic Distortion (THD) at load side is found to be 1.71%. The source voltage THD is effectively found to be 0.045%.

      10000

      dc link voltage

      5000

      0

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      time

      Compensating Load Current Harmonics Using Direct Current Control Technique

      source current

      200

      0

      -200

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      shunt

      compensating current

      2000

      0

      -2000

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      load current

      100

      0

      -100

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      Fig. 9: Simulation results mitigating the effect of temporary sag of 0.07 pu with duration 30 to 40 cycles using series voltage controller.

      (a) Supply voltage in phase-A (b) Series injected voltage in phase-A

      (c) Load voltage in phase A (d) The DC capacitor voltage

      Fig. 9(a) shows the series injected voltage, injecting the required compensating voltage. Fig. 9(b) shows the compensated feeder-2 load voltage. As can be seen from the Fig. 9(c) there is perfect compensation for temporary sag. Fig. 9(d) shows the DC link voltage. In order to supply the balanced power required to the load, the DC

      capacitor voltage drops as soon as the sag occurs. As the

      dc link voltage

      10000

      5000

      0

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

      time

      sag is removed the capacitor voltage returns to the steady state.

      The Total Harmonic Distortion (THD) at load side is found to be 1.63%. The source voltage THD is effectively found to be 0.045%.

      Compensating Load Current Harmonics Using Direct Current Control Technique

      source current

      200

      0

      The Total Harmonic Distortion (THD) at load side is found to be 1.65%. The source voltage THD is effectively found to be 0.045%.

      Compensating Load Current Harmonics Using Direct Current Control Technique

      -200

      shunt

      compensating current

      1000

      0

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      source current

      200

      0

      -1000

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      load current

      100

      0

      -100

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      -200

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      shunt compensating current

      2000

      0

      -2000

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      100

      dc link voltage

      10000

      5000

      0

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      time

      0

      load current

      -100

      dc link voltage

      10000

      5000

      0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

      Fig. 10: Simulation results- mitigating the effect of temporary sag of 0.07 pu with duration 30 to 40 cycles using direct current control technique with PI controller.

      (a) Load current in phase A (b) shunt compensating current in phase A

      (c)Supply current in phase-A (d) DC capacitor voltage The Total Harmonic Distortion (THD) at load

      side is found to be 0.479%. The source current THD was effectively found to be 14.49%.

   2. Iupqc-Mitigating The Effect Of Temporary Swell

   A 3-phase supply voltage (11kv, 50Hz) with temporary swell of .15 pu magnitude with the duration about 30 to 40 cycles is taken. With the system operating in the steady state, a 30-40 cycle temporary swell of 0.15 pu magnitude is occurring at 12 msec for which the peak of the supply reduces from its nominal value of 11kv to 12.5kv.

   0

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

   time

   Fig. 12: Simulation results- with mitigating the effect of temporary swell of 0.15 pu with duration 30 to 40 cycles using direct current control technique with PI controller.

   (a) Load current in phase A (b) shunt compensating current in phase A

   (c)Supply current in phase-A (d) DC capacitor voltage The Total Harmonic Distortion (THD) at load

   side is found to be 0.502%. The source current THD was effectively found to be 14.56%.

   Table 4: Comparison of the THD Content after Compensation in Three Different Cases of Interruptions Used For IUPQC

   source voltage

   2

   0

   -2

   series compeensating voltage

   1

   0

   -1

   load voltage

   1

   0

   -1

   dc link voltage

   10000

   5000

   0

   4

   x 10

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

   4

   x 10

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

   4

   x 10

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

   0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

   time

   Fig. 11: Simulation results with mitigating the effect of temporary swell of 0.15 pu with duration 30 to 40 cycles using series voltage controller.

   1. Supply voltage in phase-A (b) Series injected voltage in phase-A

   (c) Load voltage in phase A (d) The DC capacitor voltage

3. Conclusions

   The closed loop control schemes of Direct current control, series voltage converter for the proposed IUPQC have been described. A suitable mathematical model of the IUPQC has been developed with shunt (PI) controller and series voltage controller the simulated results have been described.

   The simulated results shows that PI controller of the shunt filter (current control mode), series filter (voltage control mode) compensates of all types of interruptions in the load current and source voltage, so as to maintain sinusoidal voltage and current at load side. The series filter was tested with different types of interruptions. The simulated results show that in all the stages of circuit operation, the feeder-2 load voltages and load currents are restored close to ideal supply.

   For all the types of disturbances (interruptions) the Total Harmonic Distortion (THD) after compensation is to be less than 5% which is as per IEEE standards.By observing below factors we conclude that performance of IUPQC for different interruptions

   1. The THD content willnot change for small term interruptions like impulsive nano, impulsive micro, impulsive milli, momentary interruption, temporary interruption etc.

   2. The THD content with sag and swell is slightly changing from 3 to 5% only.

4. References

1. A. Ghosh and G. Ledwich, Power Quality Enhancement Using Custom Power Devices. Norwell, MA: Kluwer, 2002.

2. F. Z. Peng and J. S. Lai, Generalized instantaneous reactive power theory for three-phase power systems, IEEE Trans. Instrum. Meas., vol. 45, no. 1, pp. 293297, Feb. 1996.

3. G. Ledwich and A. Ghosh, A flexible DSTATCOM operating in voltage and current control mode, Proc. Inst. Elect. Eng., Gen., Transm. Distrib., vol. 149, no. 2, pp. 215224, 2002.

4. M. K. Mishra, A. Ghosh, and A. Joshi, Operation of a DSTATCOM in voltage control mode, IEEE Trans. Power Del., vol. 18, no. 1, pp.258264, Jan. 2003.

5. H. Fujita and H. Akagi, The unified power quality conditioner: the integration of series- and shunt-active filters, IEEE Trans. Power Electron., vol. 13, no. 2, pp. 315322, Mar. 1998.

6. F. Kamran and T. G. Habetler, Combined deadbeat control of a series-parallel converter combination used as a universal power filter, IEEE Trans. Power Electron., vol. 13, no. 1, pp. 160168, Jan. 1998.

7. H. M. Wijekoon, D. M. Vilathgumuwa, and S. S. Choi, Interline dynamic voltage restorer: an economical way to improve interline power quality, Proc. Inst. Elect. Eng., Gen., Transm. Distrib., vol. 150, no. 5, pp. 513 520, Sep. 2003.

8. A. Ghosh, A. K. Jindal, and A. Joshi, A unified power quality conditioner for voltage regulation of critical load bus, in Proc. IEEE Power Eng. Soc. General Meeting, Denver, CO, Jun. 610, 2004.

9. A. Ghosh and G. Ledwich, A unified power quality conditioner (UPQC) for simultaneous voltage and current

   compensation, Elect Power Syst. Res., vol. 59, no. 1, pp. 5563, 2001.

10. A. Ghosh, G. Ledwich, O. P. Malik, and G. S. Hope, Power system stabilizer based on adaptive control techniques, IEEE Trans. Power App. Syst., vol. PAS-103, no. 8, pp. 19831989, Aug. 1984.

IX. Biographies Of Authors

B. Sasikala was born in Bapatla, A.P., India, in 1985. She completed her B.Tech from Bapatla Engineering College in 2007 and pursued her M.Tech Electrical Power Systems from St.Martins college of Engg & tech., in 2012.

She has totally 3years of teaching experience and presently working in K.G.Reddy college of engineering and technology.

Mr. Khamruddin Syed was born in Krishna District, A.P, in 1981. He completed his B.Tech from koneru Lakshmaya Engg college in 2003 and pursued his M.Tech(Power Systems) from R.V.R Engineering college, in 2006. He has five years of teaching experience. presently working as an Assistant Professor in K.G.Reddy college of engineering and technology.