Design and Development of Zero Voltage Switched Full Bridge 5 kW DC Power Supply

Design and Development of Zero Voltage Switched Full Bridge 5 kW DC Power Supply

S. K. Agrawal, S. V. Nakhe

Laser Systems Engineering Section,

Raja Ramanna Centre for Advanced Technology, Indore, India

Abstract: Design and implementation of a high power, high voltage, constant frequency, full bridge phase shift pulse width modulation converter in which zero voltage switching of all the active switches over the entire load range is maintained by using auxiliary circuit components is presented. The auxiliary circuit components used are, two capacitors that are connected in series across the DC power rail and two inductors that are connected in series with the transformer of the converter. The two capacitors act as a voltage divider providing midpoint voltage source and the two inductors supply additional current reinforcing the primary current during the transition intervals and increasing the energy available to achieve the zero voltage switching (ZVS). A prototype converter based on this topology is developed that delivers 450V at 5 kW output from 560V dc input, with efficiency greater than 94%. Experimental & simulation results for the converter are presented.

Keywords Full bridge converter, phase shift pulse width modulation (PSPWM) soft switching, zero voltage switching (ZVS), phase shift (PS), passive auxiliary circuit, ZVS range

1. INTRODUCTION

   In medium to high power DC-DC converter applications, full bridge phase shift pulse width modulation (FB-PSPWM) converters are widely used because of its fixed switching frequency ZVS operation, high efficiency, low EMI, relatively small circulating energy, utilization of output parasitic capacitance of the switches and utilization of leakage inductance of the transformer [1-3]. However, conventional FB-PSPWM converter has main drawback of limited range of operation over which the ZVS can be achieved. ZVS of the left leg switches in the conventional FB-PSPWM converter mainly depend on the energy stored in the leakage inductance of the transformer. At light load, energy stored in the leakage inductance of the transformer is not sufficient to charge/discharge the switch capacitances and this leads to loss of ZVS condition. The loss of ZVS at light loads leads to 1) High switching losses 2) Higher EMI due to high di/dt of the snubber discharging circuit. Therefore, it is desirable to maintain ZVS of the switches over the entire range of operation.

   Several techniques have been presented in literature to increase the ZVS range of conventional FB-PSPWM. Use of higher inductance in series with the transformer is reported to increase ZVS range but it leads to higher duty cycle loss as

   well as ringing across the secondary side rectifier diodes [4]. In this design higher turns ratio of transformer is required to get the desired output voltage, this results in higher primary reflected current and higher conduction loss in switches. In second technique a saturable reactor is used in series with the primary winding or with the secondary side diodes [5]. The advantage of the FB-PSPWM DC-DC converter incorporating saturable resonant inductor is that wider range of operation under ZVS is maintained without significant increase in conduction loss of the switches. However, to implement the saturable inductor large size core is required. The third technique reported to increase the ZVS for wider load range is by incorporating a commutating inductor and a clamp diode for the bridge switches [6]. However in this topology there is requirement of snubber to overcome the prevailing commutation loss. The fourth technique to increase the ZVS range in FB-PSPWM DC-DC converter is to use a two winding commutating inductor clamped to the output and overcome the problem in the technique mentioned in [6] by enabling recovery of the excess of energy directly to the load [7]. Nevertheless, this solution implies a larger, heavier and more complicated converter with inherent cost increase.

   Another method for wider ZVS range is use of auxiliary LCC circuit with conventional FB-PSPWM DC-DC converter [8, 9, 10]. The auxiliary circuit consists of a voltage divider and an inductor connected between the middle point of voltage capacitor divider and the middle point of the left leg of conventional FB-PSPWM converter. It is observed that the right leg switches leaves ZVS at lighter load compare to the left leg switches. It is desired to get ZVS for both the legs to minimize the turn-on losses including the no load condition. It is indicated that the ZVS for the both legs of FB-PSPWM DC- DC converter, can be achieved if one more inductor is used in addition to LCC circuitry described in [8,9]. This auxiliary circuit is an add-on to the conventional FB-PSPWM converter, which does not alter the power circuit.

   This paper reports the design of high power (5 kW), high voltage (450 V) FB-PSPWM converter based on LLCC auxiliary circuitry to extend the ZVS for entire load range for all the switches of full bridge without increase in the duty cycle loss. This topology is desired in applications where the output voltage is required to be adjustable and the load power is variable over a wide range. Most of the published work on

   analysis & design of FB-PSPWM converter is confined to low power (up to 3 kW) converters or to low output voltage (up to 380 V) converters. The FB-PSPWM converter reported here is rated for high voltage and high power output ( 450 V, 5 kW) with widely variable output voltage ( 1 to 100%). Description of power circuit of the FB-PSPWM converter with auxiliary circuit is presented in Section II. Modes of operation of the converter are described in Section III. Specific design considerations are covered in section IV. Simulation and experimental results are presented in section V, followed by conclusions in section VI.

2. FB-PSPWM CONVERTER WITH AUXILIARY CIRCUIT

   Power circuit diagram of the FB-PSPWM converter with LLCC auxiliary circuit is shown in Fig.1. Main FB-PSPWM converter is constituted by four MOSFET M1-M4 switches, four anti parallel diodes D1-D4, and four snubber capacitors C1-C4. The anti-parallel diodes D1-D4 across the M1-M4 are the intrinsic diodes of the respective switches. Capacitor C1-C4 across the MOSFET M1-M4 are the internal output parasitic capacitances. The average capacitance value for each of the C1-C4 is C and given as [1, 3]

   C = 4 Coss (1)

   3

   where COSS is a depletion-dependant capacity whose value depends upon the impressed drain -source voltage across the

3. MODES OF OPERATION

   Key waveforms of the FB-PSPWM converter with LLCC auxiliary circuit are shown in Fig.2. In these waveforms the voltages Vg1-Vg4 are the gate voltage signals for switches M1- M4 respectively and have approximately 50% duty cycle. These signals are generated using standard Phase shift controller UCC3895 [11]. The switches of left leg (M1 & M2 ) and right leg (M3 & M4) turn-on and off alternatively with a small dead time between the gate pulses of each leg to allow the capacitor to discharge before the switches are made on. The phase shift between the two legs determine the operating duty cycle of converter. The operation of converter presented in Fig.1 is explained for positive cycle of primary current with five modes. Mode I or power delivery mode, Mode II or powering to freewheeling transition mode, Mode III or freewheeling interval, Mode IV or freewheeling to powering transition interval and Mode V or linear transition mode.

   Mode I: Power delivery mode (t0 < t t1):

   During this mode both M1and M4 are in conduction and Dr1 & r4 are rectifying. The transformer primary voltage is Vd and the primary current increases with the slope proportional to the total inductance present in the circuit. In this interval power is delivered to load, hence known as power delivery interval. Primary current during this interval is given by

   = 0 + 0 (3)

   respective MOSFET.

   0

   Transformer TR has primary to secondary turn ratio of n:1. Total leakage inductance of the transformer referred to primary is Llk. The voltage across the primary winding of transformer is VAB and the voltage across the secondary winding is VS. Dr1- Dr4 are the diodes on the secondary side forming full bridge rectifier circuit. Inductor Lf and capacitor Cf form the output filter.

   In conventional FB-PSPWM converter the energy stored in the leakage inductor is used to charge/discharge the snubber capacitors, and the load range under which ZVS of the switches is maintained strongly depends on the value of the leakage inductance. Due to leakage inductance, there is duty cycle loss D and it is given as [3]

   where Ip(0) is the initial value of the primary current and Leq = Llk + n2 Lf

   The mode interval ends when the primary current reaches to its peak value I1.

   1 = 1 (4)

   During this mode the terminal A of auxiliary inductor L1 is connected to Vd and voltage across L1 is -Vd/2 and current through L1 decreases until the MOSFET M1 turns off. Similarly B terminal of inductor L2 is connected to ground, hence the voltage across L2 is Vd/2 and current increases and reaches to its peak value IL2 at the end of this interval i.e. when M4 turns-off. The auxiliary circuit acts as independent circuit

   without influencing the primary current. Currents through

   4

   (2)

   auxiliary inductor L1 & L2 are given as:

   Ts

   = +

   0 (5)

   where Ts is switching period of converter, Vd is the input DC

   1

   21

   0 1

   voltage, Io is output dc ( average) load current.

   =

   +

   0 (6)

   The auxiliary LLCC circuitry that provides ZVS over the

   2

   22

   0 2

   entire load range consists of two inductor L1 & L2 and two capacitors Cd1 & Cd2. The two capacitors with equal

   capacitances are connected in series, across the DC power rail Vd and this forms a voltage divider circuit. Out of the two

   where 1 (0), 2 (0) are the initial value of the currents of auxiliary inductor L1 & L2 respectively.

   Current through the inductor L2 at the end of this mode is

   auxiliary inductors, one inductor L1 is connected between

   =

   =

   (7)

   middle point A of left leg and the middle point M of capacitor divider. The second inductor L2 is connected between middle Or

   2 1

   42 2

   2

   point B of right leg and the middle point M of the capacitor

   . ;

   (8)

   divider.

   2

   82

   2

   RCD clamp circuit is used to reduce ringing and voltage overshoot across the diode rectifier, arising because of resonance between the stray capacitance (due to winding & diode) and the leakage inductance of the transformer [1].

   is known as right leg transition interval or powering to freewheeling transition interval.

   The drain current of M1 is sum of the primary current and auxiliary inductor current IL1. Similarly the drain current of M4 is the sum of the primary current and auxiliary current IL2.

   Left Leg Right Leg

   Lf IO

   Cd1

   Vd M

   Vg1 L1

   iL1

   M1 D1 C1

   ip

   A

   L2

   Vg3

   M3 D3 C3

   Llk

   B

   TR

   n:1

   Dr3

   +

   VS

   Dr2

   Dr1

   –

   Dc

   Rc

   Cf

   RCD

   +

   RL Vo

   –

   C M D

   iL2

   C

   M D C

   Dr4

   Clamp Circuit

   d2

   Vg2

   2 2 2

   Vg4

   4 4 4 CC

   Fig.1 Full bridge phase shift PWM DC-DC converter with auxiliary LLCC circuit

   Vg 1

   t

   Vg 2 TS

   t

   Vg 3

   Vg 4 t

   VAB t

   Vd

   t

   I1

   ip

   t LL

   t

   tRL

   VS

   iL1 IL1

   t

   DTs/2

   t

   iL2

   IL2

   t

   t0 t1 t2

   t3 t4 t5

   Ts+ t0

   Fig.2 Key waveforms of the Full bridge phase shift PWM DC-DC converter with the auxiliary circuit

   Mode II: Powering to freewheeling transition mode (t1 < t t2):

   =

   (4)2

   2 ( ) +

   (1)2

   2 ( 1 ) (14)

   This mode starts when MOSFET M4 turns off at time t1. As

   M4 turns off, drain current of M4 is transferred to C3 & C4. Since M1 is conducting and M4 is off, transformer continues to see the positive voltage Vd during this interval. Hence Dr1& Dr4 are still conducting as in mode I. The duration of this mode is small, so the primary current and the auxiliary inductor current IL2 is almost constant. Hence the charging of C4 and discharging of C3 takes place linearly. The time required to complete charge/discharge is given as

   where I4 is the primary current at t = t4 and IL1 is the peak current of the auxiliary inductor L1.

   This mode ends when the capacitor C1 voltage reaches to Vd and capacitor C2 voltage reaches to zero and diode D2 starts conducting at time t4. Current in inductor L2 during this mode is still given by eq. (13).

   Mode V: Linear mode (t4< t t5):

   At time t4 diode D2 initiate its conduction. In this mode

   . ( 3 + 4)

   1 + 2

   2. .

   1 + 2

   (9)

   primary current changes its polarity. Till the primary current reaches to zero, diode D2 & D3 conduct, thereafter M2 & M3

   Since M1 is still on, the current in L1 is given by eq.(5). This start conducting. Primary current in this interval is given as

   mode ends when the capacitor C3 voltage reaches to zero and diode D3 start conducting at t = t2 with ZVS.

   =

   4 + 2 (15)

   Mode III: Freewheeling mode (t < t t ):

   where (2) is the initial value of the primary current.

   2 3 In this mode terminal A of auxiliary indictor L1 is

   This mode starts with zero voltage across capacitor C3 and diode D3 initiates its conduction. Primary current freewheels through the MOSFET M1 & diode D3. The voltage across the

   connected to ground as M2 is on. The voltage across the L1 is Vd/2. The current in L1 starts increasing and given by

   = + 1 (16)

   primary of transformer VAB is zero. The rectifier diodes Dr1&

   Dr4 are still in conduction state. The circuit enters the passive

   1

   21

   4 1

   mode i.e. no power is transferred from input to output. This mode ends when gate pulse of M1 is removed. Primary current during this mode is given by

   = 0 + 1 (10)

   where 1 (1) is the initial value of the primary current.

   The time interval of this mode represents the duty cycle

   loss. In order to reduce the duty cycle loss the slope of primary current should be high i.e. leakage inductance should be

   2

   minimum. In conventional PSPWM converter, leakage

   where (1) is the initial value of the primary current.

   As the M1 is on, current in L1 is still given by the equation (5). It reaches to its peak value IL1 at the end of the interval and

   inductance needs to be kept large to store sufficient energy to achieve ZVS of switches for wider range while in the

   proposed converter, the value of leakage inductance is small and limited by construction of transformer which leads to

   given by.

   Or

   1 3 =

   41

   = 2 1

   (11)

   lower duty cycle loss.

   Further for the negative half cycle of primary current these five modes of operations are similarly repeated and the full cycle is complete.

   . ;

   (12)

   1

   81

   2

   where is known as left leg transition interval or freewheeling to powering transition interval The current in L2 start decreasing from its peak value and given as

4. DESIGN CONSIDERATIONS

   Zero voltage switching for the left leg switches (M1 & M2) always takes place when the output current source is

   =

   +

   (13)

   freewheeling through the output diodes. Thus the available

   2

   22

   3 2

   energy, to perform the discharge and charge of capacitor C1/C2 within left leg interval tLL, is stored in auxiliary inductor L1 and

   Mode IV: Freewheeling to powering transition mode (t3< t

   t4):

   This mode starts at time t3 when the gate signal of M1 is removed. At this stage D3 is still conducting and primary

   the leakage inductor. Thus the condition for achieving ZVS for this leg is, stored energy in inductors should be greater than the energy stored in the capacitors C1 and C2.

   = 1 2

   Energy stored in Capacitors C1 and C2 is

   current is same as it was in mode III, and flows through C1 &

   1 ( + ). ( )

   2

   2 = . ( )2 (17)

   C2. During this mode, contrary to what happened in mode II,

   all four diodes of rectifier are on. Therefore energy stored in

   Energy stored in inductors Llk and L1 is

   ( /)2 2

   the filter inductor does not contribute to charge/ discharge of

   = 0 .

   + (1)

   .

   (18)

   C /C . Because of this reason it is very difficult to obtain ZVS

   2

   2 1

   1 2

   in the conventional converters for light load. However in the converter design presented here, additional energy is stored in inductor L1 in mode I to III, that helps to achieve ZVS. Thus the total energy (WL) available to charge/discharge the capacitor C1/C2 is the energy stored in leakage inductor of transformer and energy stored in the auxiliary inductor L1.

   In the expression of stored energy in inductors, the first term represents stored energy in the leakage inductor due to load current and the second term represent energy stored in auxiliary inductor L1 due to current IL1 in it. Hence to achieve ZVS

   (0/)2

   2 +

   (1)2

   2 1 ( )2

   (19)

   The main parameters and component values used for simulation as well as in the experimental setup can be

   From equation (12) & equation (19)

   obtained from the design procedure presented in section IV

   (0/)2

   2 +

   ( )2 ( )2 2

   1281 ( )

   (20)

   and [1,3]. Parameters and components based on the specifications for the FB-PSPSWM dc-dc converter under

   consideration are given in table I.

   Design efforts should be made to minimize the leakage

   inductance such that there is minimum duty cycle loss. This also results in minimum voltage overshoot and ringing on the secondary side. To achieve ZVS for the left leg switches independent of load, energy stored in inductor L1 must be higher than the energy stored in capacitor C1 & C2 hence condition for achieving ZVS independent of the load can be obtained by putting 0 = 0 in eq. (20)

   ()2

   1 128 (21)

   TABLE I : Parameters and components of the simulation and

   experimental circuit

   Component/Parameter	Value
   M1 – M4	IXFN44N80
   Dr1- Dr4, Dc	DSEI2x61-10b
   TR	Turn ratio = 0.83:1, Using four Mn-Zn U 93/76/30 ferrite core
   Leakage Inductance Llk	50 µH
   C1-C4	1729 pF
   tLL, tRL	700 ns
   Lf	1.8 mH
   Cf	50 µF
   L1	350 µH
   L2	350 µH
   Cd1,Cd2	1 µF
   Rc	10 k
   Cc	0.47µF

   Another condition for selection of auxiliary inductor L1 is

   based on the time interval tLL allowed to charge / discharge the snubber capacitor

   1

   16

   (22)

   Hence, value of L1 that provide the ZVS of left leg switches for entire load range can be obtained by satisfying the eq. (21) & (22).

   Zero voltage switching for right leg switches (M3 & M4) takes place when the reflected output current in primary is present. The total current which is available to charge and discharge the capacitor C3/C4 linearly within right leg interval tRL is sum of the peak primary current 1 and auxiliary inductor current IL2. Condition for achieving ZVS for the right leg switches is

   1

   + 2

   (3 + 4)

   (23)

   Hence to ensure the ZVS for right leg switches independent of load, value of IL2 is given as

   (3 + 4) ;

   2

   (24)

   The simulated and experimental waveforms of primary

   2

   2

   current of the transformer at load current of 10.6 A and at

   The value of L2 for achieving ZVS for right leg switches independent of load can be obtained by using eq. (24) & (8)

   input voltage of 560 V with and without auxiliary circuit are shown in Fig.3a and Fig.3b respectively. From results it is

   clear that these waveforms are identical and hence it is

   and given as

   2

   (25)

   confirmed that there is no additional duty cycle loss with the auxiliary circuit.

   16

   20 I I 10 0 -10

   (T (T

   X1 X1

   :1) :2)

   With With

   au out

   xilia aux

   ry i ilia

   ndu ry i

   cto ndu

   r ctor

   -20 1.800ms 1.810ms 1.820ms I(TX1:1) I(TX2:1) Time

   Fig.3a: Simulated waveform for primary current of transformer at full load with and without auxiliary circuit

   Output Voltage of the proposed converter is

   0

   =

   (26)

   given as

   is effective duty cycle of the converter and

   = (27)

   where D is the duty ratio of the primary voltage of transformer.

5. SIMULATION & EXPERIMENTAL RESULTS

   To verify the proposed LLCC auxiliary circuit, a 5 kW DC-DC converter is designed to meet the following specifications: Input voltage Vd = 560 V, (standard full wave rectified voltage of 415 V, 3 phase), adjustable output voltage, Vo = 0-450 V DC, switching frequency fs = 50 kHz and ZVS for 0-100% of full load.

   IInntteerrnnaattiioonnaall JJoouurrnnaall ooff EEnnggiinneeeerriinngg RReesseeaarrcchh && TTeecchhnnoollooggyy ((IIJJEERRTT))

   ISSN: 2278-0181

   Vol. 3 Issue 5, May – 2014

   switching losses. Under this condition the switch will damage and to protect it switches with higher current rating are required.

   200

   100

   0

   VD

   S

   of

   M2

   ID

   S

   of

   M2

   Fig.3b: Experimental waveform of primary current at full load of transformer with (Red) and without (Yellow) auxiliary inductors; X axis (5µs/div), Y axis (5A/div)

   200

   I(M2:d) V(M2:d)/10

   ID

   S

   of

   M4

   1.820ms

   1.810ms

   M4

   f

   o

   VGS

   M4

   of

   S

   VD

   0

   S

   VG

   100

   0

   1.800ms

   4

   M

   f

   o

   DS

   V

   The gate-source and drain-source voltage waveform of left leg switch M2 and right leg switch M4 are shown in Fig.4a and 4b. The waveforms confirm the ZVS operation of all the switches, as the gate-source voltage appears after the drain- source voltage drops to zero.

   20

   10

   0

   -10 V(M2:d)/10

   20

   10

   0

   -101.800ms

   of

   M2

   V

   DS

   o

   f

   M

   2

   V(M4:d)/1 V(M4:g) Time

   Fig.4a: Simualted waveform for gate-source voltage VGS (5V/div) and drain-source voltage MOSFET M2 & M4

   VDS of M2

   VGS of M2

   VDS of M4

   VGS of M4

   Fig.4b: Experimental waveform for gate-source voltage VGS (5V/div) and drain-source voltage VDS (200V/div) M2 (Upper) & M4(Lower); X axis (5µs/div)

   Simulated waveforms for drain – source voltage and drain current of MOSFET M2 & M4 at 8% of full load current without auxiliary circuit are shown in Fig.5. From the waveforms it is clear that there is no ZVS for the switches at light load. There is high peak current through the switches at light load without auxiliary circuit which results in high

   I(M4:d) V(M4:d)/10 Time

   Fig.5: Simualted waveform for drain-source voltage and drain current of MOSFET M2 & M4 without LLCC auxiliary circuit

   1.820ms

   1.810ms

   Experimental waveforms of current through auxiliary inductor L1 and L2 are shown in Fig.6. The peak current supplied by inductors is 3.6 A for input voltage of 560 V. This additional current is supplied to get the ZVS at light load or no load for left leg and right leg.

   Fig.6: Experimental waveform for current in auxiliary inductor L1 (Upper) & L2 (Lower); X axis (5µs/div),Y axis (2A/div)

   The simulated and experimental drainsource voltage and drain current waveforms of the switch M2 of left leg & M4 of right leg at 95% of full load and 450V output with LLCC auxiliary circuit are shown in Fig.7a and 7b respectively. Similarly the simulated and experimental drainsource voltage and drain current waveforms of the switch M2 of left leg & M4 of right leg at 8% of full load and 450V output with LLCC auxiliary circuit are shown in Fig.8a and 8b respectively. Since in all the waveform drain current through the switch crosses the zero after drain-source voltage of switch drops to zero. Hence ZVS of all the switches over the entire conversion range is demonstrated.

   Output rectifier waveforms with or without RCD clamp circuit are shown in Fig.9 for input voltage of 385V. Without RCD clamp circuit, there is overshoot of 380 V on rectifier voltage, while with RCD clamp circuit the overshoot is 100 V.

   VD

   S

   of

   M2

   ID

   S

   of

   M2

   VDS of M2

   IDS of M2

   ID

   S

   of

   M4

   V

   DS

   o

   f

   M

   4

   VDS of M4

   IDS of M4

   1.800ms

   V(M4:d)/1

   1.810ms

   1.820ms

   Fig.7a: Simulated waveforms for drain-source voltage and drain current of MOSFET M2 & M4 with auxiliary circuit at 95% of load current

   IDS of M2

   VDS of M2

   Fig.8b: Experimaental waveform for drain -source voltage and drain current of MOSFET M2 & M4 with auxiliary circuit circuit at 8% of full load; X axis (2µs/div) ,Y axis (VDS: 200V/div, IDS :2A/div).

   Without RCD clamp circuit

   IDS of M4

   VDS of M4

   With RCD clamp circuit

   Fig:9: Output rectifier waveform (X- axis 200V/div, Y-axis 2µs/div)

   Fig.7b: Experimaental waveform drain-source volatge and drain current of MOSFET M2 & M4 auxiliary circuit at 95% of load current; X axis (5µs/div) ,Y axis (VDS: 200V/div, IDS (10A/div))

   Time

   I(M4:d)

   -40

   80

   40

   0

   -40 V(M2:d)/10 I(M2:d)

   80

   40

   0

   IDS of M2

   5.0

   VDS of M2

   0

   -6.0

   I(M2:d) V(M2:d)/100

   IDS of M4

   5.0

   VDS of M4

   0

   –

   1.800ms 1.810ms 1.820ms

   I(M4:d) V(M4:d)/100 Time

   Fig.8a: Simualted waveforms for drain-source voltage and drain current of MOSFET M2 & M4 with auxiliary circuit at 8% of full load.

   The improvement of efficiency with proposed converter compare to conventional PSPWM converter at light loads depends on switching losses saved by achiveing ZVS operation and the additional conduction losses in the switches due to circulating current and losses in inductor. The saving in switching losses achieved by this ZVS scheme will be very effective for the converters operating at higher swithcing frequency or in higher power converters (> 5 kW) where the snubber capacitors are large (tens of nano-farads).

   The efficiency of the FB-PSPWM DC-DC converter developed is around 94% under full power ( 5 kW) output condition that is with input voltage of 560 V, and output voltage 450 V. The efficency is calculated based on measurement of input and output DC volatge and current.

6. CONCLUSION

Design, simulation and performance of a high power (5 kW), high voltage dc to dc converter based on modified Full Bridge Phase- Shift PWM topology is presented here that provides zero voltage switching of the switches over the full range of output load. The converter has efficiency of 94% at

full load under nominal input voltage. The modification over conventional Full Bridge Phase Shift PWM DC-DC converter is use of two inductors and two capacitors forming an auxiliary circuit. This enables the converter to achieve zero voltage switching of all the switches independent of load conditions. The simulation and experimental results of the converter demonstrated zero voltage switching over the entire conversion range without any additional duty cycle loss. The only disadvantage of the proposed converter is small increase of the peak current in the switches. This design can be easily adopted for high power DC-DC converter.

REFERENCES

1. J.A. Sabate, V.Valtkovic, R.B. Ridley, F.C. Lee and B.H. Cho, Design Considerations for high-voltage high-power full-bridge zero- voltage-switching PWM Converter, IEEE APEC, pp.275-284.

2. M. Brunoro and J. L. F. Vieira, "A high performance ZVS full-bridge dc-dc 0-50V/0-10A oiwer supply with phase-shift control", IEEE PESC Conf. Rec., pp.262 -268 1997.

3. D. J. Hamo, "A 50W, 500kHz, Full-Bridge, Phase-Shift, ZVS Isolated DC to DC Converter Using the HIP4081A," Application note 9506,

   Harris, 1995. www.intersil.com/data/an/an9506.pdf

4. B. Andreycak, "Design review: 500W, 40W/in3 phase shifted ZVT power converter ", Unitrode Power Design Seminar SEM-900

5. G. Hua, F. C. Lee, and M. M. Jovanovic, An improved full-bridge zero- voltage-switched PWM converter using a saturable inductor,IEEE Trans. Power Electron., vol. 8, no. 4, pp. 530534, Oct. 1993

6. Redl, L. Balogh , D.W. Edwards, Switch transitions in the soft- switching full bridge PWM phase – shift dc/dc converter: analysis and improvements, Proc. INTELEC 93, pp 350-357

7. S.Valtchev, B. Borges, Improved full bridge zero voltage switched phase shift DC/DC converter using a secondary clamped inductor,

   IEEE Industry Electronics Conference, IECON95, pp. 258 – 264

8. 8. J. P. Beirante and B. V. Borges, A New Full Bridge Zero Voltage Switched Phase Shifted DC-DC Converterwith Enlarged Duty Cycle and ZVS Range, Conference of CONTELE, pp. 136, 2001. http://www.co.it.pt/conftele2001/proc/pap136.pdf

9. D.K Jain, P.K Jain, Haibo Zhang – Analysis and design of an auxiliary commutated full bridge DC/DC converter topology including the effect of leakage inductance, Telecommunications Energy Conference, INTELEC, 2002. 24th Annual International, pp 240-247 http://bbs.dianyuan.com/bbs/u/30/1120055190.pdf

10. Dheeraj K. Jain, Analysis and design of an auxiliary commutated full bridge dc/dc converter for low voltage and high current applications, M.A.Sc. Thesis, In the Department of Electrical and Computer Engineering, Montreal, Canada, December 2001.

11. Datasheet of BiCMOS Advanced phase shift PWM Controller UCC3895 http://www.ti.com/lit/gpn/ucc3895