Design and Implementation of 4-bit Array Multiplier for Low Power in 45nm CMOS Technology

Design and Implementation of 4-bit Array Multiplier for Low Power in 45nm CMOS Technology

Khushbu Maheshwari

Electronics & Communication department

Shri Satya Sai Institute of Science and Technology RGPV University

Sehore, Bhopal, MP, India

Prof. Mukesh Tiwari Electronics & Communication department

Shri Satya Sai Institute of Science and Technology RGPV University

Sehore, Bhopal, MP, India

Abstract This paper will represent the design and implementation of 4 bit Array Multiplier, using four different CMOS topology as static or conventional CMOS, Gate diffusion input(GDI), Low Power Feed Through Logic(LP-FTL) and High Speed Feed Through Logic(HS-FTL). Adder is the basic building for all arithmetic operations like addition, subtraction and multiplication, we have implemented the 4 bit Array multiplier in BPTM 45nm CMOS technology in LT spice IV.

KeywordsCMOS, GDI, BPTM, HS-FTL, LP-FTL

1. INTRODUCTION

   Multiplier plays a significant role in high speed digital signal processing. Its the most important part of the Arithmetic Logic Unit (ALU), FPU and ASICs where high processing speed is required. Currently, the importance of low power design increases rapidly due to the increasing demand for portable and mobile systems.

   High performance dynamic circuits due to their compactness and higher speed as compared to static CMOS

   [1] are increasingly being used, mainly in wide fan in circuits. However the major drawback with this logic is its excessive power dissipation due to the switching activity and clock, also it suffers from charge leakage, charge sharing and requirement of additional output inverter during cascading of logic blocks. As we know Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc.

   Power consumption and its minimization is one of the primary concerns in today VLSI design methodologies because of two main reasons one is the long battery operating life requirement of mobile and portable devices and second is due to increasing number of transistors on a single chip leads to high power dissipation and it can lead to reliability and IC packaging problems.

   A 4×4 bit Array multiplier is constructed as the basic building block for higher order multipliers. In Fig. 1 the sketch diagram of the multiplier and 4 bit array architecture is shown with two major blocks as AND gate logic and 1-bit

   full adder in Fig. 2. Let A0 A3 be the word length of multiplicand, and B0 B3 be the word length of the multiplier. After multiplication we can observe the P0 – P7 are final results. During the whole process we found that we can built multiplier with help of 1 bit full adder and basic AND gate logic.

   Fig.1 4-bit Multiplier Structure

   Fig. 2 4-bit Multiplier Architecture

2. IMPLEMENTATION OF 4 BIT ARRAY MULTIPLIER

   1. Conventional CMOS Logic

      As the static or conventional CMOS style is the basic style used in VLSI implementation and basic logic for the development in power reduction technology. A 4 bit CMOS

      array block representation shown in figure 3 and its simulation result shown in figure 4 and figure 5 respectively.

   2. Gate Diffusion Input(GDI)

      A new low power design technique that solves most of the problems known as Gate-Diffusion-Input (GDI) is proposed. This technique allows reducing power consumption, propagation delay, and area of digital circuits. A basic GDI cell contains four terminals G (common gate input of nMOS and pMOS transistors), P (the outer diffusion node of pMOS transistor), N (the outer diffusion node of nMOS transistor), and D (common diffusion node of both transistors). As shown in figure 7 and figure 8 we can observe the simulation results for the Gate Diffusion input array multiplier.

      Fig. 3 Block diagram of 4-bit CMOS Array Multiplier

      Fig. 4 Simulation result for 4-bit CMOS Array Multiplier (P0 P3)

      Fig. 5 Simulation result for 4-bit CMOS Array Multiplier (P4 P7)

      Fig. 6 Block diagram of 4-bit GDI Array Multiplier

   3. Feed Through Logic

   A feed through logic is a widely used Dynamic logic for power reduction in VLSI designs. It has two types one is for low power and second for the high speed so we had implemented both architecture as shown in figure 9, figure 10 and figure 11 shows for the low power feed through logic (LS-FTL), where figure 12, figure 13 and figure 14 shows for the high speed feed through logic (HS-FTL).

   Fig. 7 Simulation result for 4-bit GDI Array Multiplier (P0 P3)

   Fig. 8 Simulation result for 4-bit GDI Array Multiplier (P4 P7)

   Fig. 9 Block diagram of 4-bit LPFTL Array Multiplier

   Fig. 10 Simulation result for 4-bit LPFTL Array Multiplier (P0 P3)

   Fig. 11 Simulation result for 4-bit LPFTL Array Multiplier (P4 P7)

   Fig. 12 Block diagram of 4-bit HSFTL Array Multiplier

   Fig. 13 Simulation result for 4-bit HSFTL Array Multiplier (P0 P3)

   Fig. 14 Simulation result for 4-bit HSFTL Array Multiplier (P4 P7)

3. COMPARATIVE ANALYSIS OF 4 BIT ARRAY MULTIPLIERS

As shown in the table 1 demonstrate the power consumption and integral power delay product of all 4 bit array multiplier. We found that Lop Power Feed through Logic (LP-FTL) has the least power dissipation compared to the GDI and static CMOS logic adder and High Speed Feed through Logic (HS- FTL).

TABLE I POWER DISSIPATION AND POWER PRODUCT DELAY OF 4 BIT

ARRAY MULTIPLIERS

ACKNOWLEDGMENT

I would like to say thanks to my guide Prof. Mukesh Tiwari sir for their kind support throughout the work, and I am also thank full to Prof. Jay Karan Singh for their noble support in completing this work.

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