Design and Implementation of Integer-N Frequency Synthesizer using 45nm CMOS Technology

Design and Implementation of Integer-N Frequency Synthesizer using 45nm CMOS Technology

Shreya K B

Department of Electronics and Communication, VVCE, Mysuru, Karnataka, India,

Kiran K R

Department of Electronics and Communication, VVCE, Mysuru, Karnataka, India,

Jayashree B V

Department of Electronics and Communication, VVCE, Mysuru, Karnataka, India

K R Prathiksha Rohini

Department of Electronics and Communication, VVCE, Mysuru, Karnataka, India,

Rohith K

Department of Electronics and Communication, VVCE, Mysuru, Karnataka, India,

Shyma zaidi

Department of Electronics and Communication, VVCE, Mysuru, Karnataka, India

AbstractThis paper proposes an inductor-less frequency synthesizer.This PLL based synthesizer uses ring oscillators for VCO. This system generates various frequencies using one reference frequencyfor attuning in communication system. An inductor based VCO has large area and low Q factor so by implementing an inductor less VCO by using ring oscillators which is a series combination of CMOS inverters, the area of the chip is optimized. The synthesizer is designed in GPDK045 library of 45nm processto operate in the range of 1 GHz to 2.3 GHz and itexhibits an in-band phase noise of -97.2 dBc/Hz with a lock time of 3.2ns.

Keywords-Frequency synthesizer, (Phase Locked Loop) PLL, (Voltage Controlled Oscillator) VCO, (Phase Frequency Detector) PFD, (Charge Pump-Loop Filter) CP-LF, Divider CMOS ring oscillator.

typically sinusoidal or digital clock. A basic PLL is a negative feedback system that consists of a phase detector, a low pass loop filter and a voltage-controlled oscillator (VCO) as shown in figure 1.

Section II describes the components of the synthesizer. In Section III, the performance parameters are outlined. The result of the simulated study is defined in Section IV.

1. INTRODUCTION

   A frequency synthesizer (a system of frequency synthesis) provides a way for generating the array of high-stable frequencies for synchronization ofcommunication systems and support of multifrequency operating mode. The recent growth in wireless communication systems has raised the demand for more channels in mobile communication applications. As, we defined in the high frequencystandards, such as in various wireless communications which includes WiGig, WirelessHDetc., To achieve a higher data rate, complex modulations such as CSVCO (Current Starved Voltage Controlled Oscillator) is adopted, whichincreases the requirements of the oscillators phase noise and phase error. For past few years, ithas already been demonstrated that advanced CMOS technology can realizedifferent wave ICs. CMOS implementation reduces cost and improves yield,as the RF front-end integrates with analog and digital baseband circuits.

   A frequency synthesizer is also called as a PLL synthesizer. A PLL is a device which locksan output signal phase in accordance with the input reference signal phase. The signals of interest may be any periodic waveform but are

   Fig.1. A Conceptual synthesizer with inductor-less VCO.

2. LITERATURE SURVEY

   The author in [1] describes an architecture of the frequency synthesizer which has no inductor hence achieving an in-band low phase noise of 109 dBc/Hz. It is realized using a 45nm CMOS technology incorporating an analog noise trap to suppress the quantization noise. The design reduces the loop bandwidth, increasing the locking time by a considerable proportion.

   In [2] the author talks about a system where the numerical evaluations of the response speed and the stability of hybrid frequency synthesizersare obtained. The lowest level of spurious spectral components in wireless communication systems are provided. This proposal is only achieved in a mathematical model.

   In [3] author describes a design realized in 45-nm CMOS technology to suppress reference sidebands to less than -65 dBc while consuming 4 mW of power. The wideband architecture has been successfully extended to a Fractional-N loop as well. The chip size is reduced with low noise levels but the designing is difficult

   In [4]author describes an in-band phase noise of 112 dBc/Hz and a reduced reference spur and power requirement suitable for wireless communication applications. It provides a lock time of 2.95 s. The design is realized using 180nm CMOS technology which is a drawback.

3. PROPOSED METHODOLOGY

   1. Phase Frequency Detector (PFD)

      Phase frequency detector is an important part of the PLL circuit. PFD is a circuit that measures the difference in phase and frequency of two signals, i.e., the signal that comes from the VCO, and the reference signal.PFD has two outputs UP(QA) and DOWN(QB) which are signaled according to the phase and frequency difference of the input signals. Figure 2shows a PFD with its inputs and outputs.

      Fig .2. Detailed block diagram of PFD.

      The PFD consists of two D flip flops and an AND gate. As the fig 2 showsthe D input of the flip-flops is connected to VDD and the input signals Cref(A) and cvco(B) are applied to the clock input. When one of the clocks switches to logic high, thisflip-flop will be charged and changes its output to high. The AND gate is used for preventing bothflip-flops to be high at the same time. The design of the schematic of PFD is shown in fig. 3.

      Fig. 3. Schematic of a PFD

   2. Charge Pump and Loop Filter

      Charge pump is the circuit that translates the UP and DOWN signals from thePFD to control voltage that will control the VCO. As shown in figure4, charge pump consists of two switched current sources driving a capacitive load. Charge pump is switched on and off by the PFD output signals UP and DOWN.As shown in fig. 5, the schematic of the charge pump shows the output signals UP and DN.

      The design of the PLL, loop filter is crucial to the operation of the whole phase locked loop. The choice of the circuit sizes and values here is done very carefully with balanced compromise between number of requirements.

      The PLL filter is used to remove any unwanted high frequency components which may pass out of the phase detector and appear at the VCO input. They would then appear at the output of the VCO, as spurious signals.

      Fig. 4. Charge Pump and loop filter in PLL

   3. Ring Osciallator in VCO

      Use of LC tanks in the design of VCO (Voltage Controlled Oscillator) acquires large chip area and has low Q factor. Oscillators based on LC tanks have low frequency tuning range and the required frequency of operation may not reside in the limited tuning range as the temperature varies. Therefore, inductor less oscillators are under tremendous research.

      (1)

      Fig. 5. Schematic of a charge pump

      The use of CMOS ring oscillators is the best alternative to overcome the LC tank drawbacks. Due to the absence of LC tanks, the general Q factor considerations as per equation (1) are no longer valid. In case of LC resonators, the capacitor stores electrical energy and the inductor stores the magnetic energy. Meanwhile, some of the energy is dissipated through the resistor connected in parallel. The definition of Q factor in equation (1) does not apply to ring oscillators.

      Fig. 6. Schematic of a simple 5- ring oscillator

      A ring oscillator is a device composed of an odd number of NOT gates whose output oscillates between two voltage levels, representing true and false. A schematic diagram of a simple five inverter ring oscillator is shown in Fig.4.

      A single inverter computes the logical NOT of its input, it can be observed that the last output of a chainof an odd number of inverters is the logical NOT of the first input. The final output is asserted a finite amount of time after the first input is asserted and the feedback of the last output to the input causes oscillation.This final output is asserted a finite amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation. A real ring oscillator only requires power to operate; above a certain threshold voltage, oscillations begin spontaneously. To increase the frequency of oscillation, the applied voltage may be increased; this increases both the frequency of the oscillation and the power consumed, which is dissipated as heat.

      Fig. 7. A transistor level schematic of a five-stage ring oscillator

   4. N-Integer Divider

   It is a circuit which divides the output frequency by an integer value so that the input reference clock frequency is comparable with the VCO generated frequency. The output of the VCO is fed back to the PDF through the frequency divider circuit and forms a closed loop. Figure 8, shows the schematic of the frequency divider circuit.

   Fig. 8. Schematic of integer divider circuit

4. EVALUATION/PERFORMANCE PARAMETERS

   Fig. 9. Power consumption is measured to be 1.76 mW

   Fig. 10. Measured phase noise at 2.3GHz

   The simulation result of phase noise is shown in figure 10. The phase noise of this circuit is -97.2 dBc/Hz. This was simulated using ADE L in Cadence. And the locking time of the PLL is measured to be 3.2ns at 2.3GHz using Spectre simulator in Cadence. This is shown in figure 11. The power consumption measured in the same tool is 1.76mW as shown in figure 9.

   Fig. 11. Measured lock time is 3.2ns at 2.3GHz

5. RESULTS

The Integer-N synthesizer is designed in 45-nm digital CMOS technology. The die measures around 66um x 52um. It operates within the range of 1 GHz to 2.3GHz with a phase noise of -97.2 dBc/Hz, which satisfies IEEE standards. The power consumed by the whole circuit is 1.76 mW at 2.3 GHz.

ACKNOWLEDGMENT

This paper was supported by Head of Department Dr. D J Ravi and project guides Prof. Rohith K, department of Electronics and Communication, Vidyavardhaka College of Engineering, Mysuru.

REFERENCES

1. L. Kong and B. Razavi, A 2.4-ghz 6.4-mw fractional-n inductorless rf synthesizer, in 2016 IEEE Symposium on VLSI Circuits (VLSI- Circuits), June 2016, pp. 12.

2. A. M. Pilipenko, Simulation and parameters optimization of hybrid frequency synthesizers for wireless communication systems, in 2017 International Siberian Conference on Control and Communications (SIBCON), June 2017, pp. 16.

3. L.Kong, RF Synthesis without Inductor, UCLA Theses and Dissertations, Jan 2016.

4. P. C. Huang, W. S. Chang, and T. C. Lee, A 2.3ghz fractional-n dividerless phase-locked loop with -112dbc/hz in-band phase noise, in 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), Feb 2014, pp. 362363.

5. L. Kong and B. Razavi, A 2.4ghz rf fractional-n synthesizer with 0.25fref bw, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), Feb 2017, pp. 330331.

6. C. H. Son and S. Byun, On frequency detection capability of full-rate linear and binary phase detectors, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 7, 2017, pp. 757761.

7. T. P. Wang, W. B. Lu, T. S. Chu, and S. H. Lin, Design of low-voltage low-power 40-ghz cmos vco, in 2017 IEEE International Conference on Consumer Electronics – Taiwan (ICCE-TW), June 2017, pp. 421 422.

8. X. Deng, Y. Mo, X. Lin, and M. Zhu, Low-jitter all-digital phase- locked loop with novel pfd and high resolution tdc dco, in 2016 29th IEEE International System-on-Chip Conference (SOCC), Sept 2016, pp. 2934.

9. L. Kong and B. Razavi, 25.7 a 2.4ghz 4mw inductorless rf synthesizer, in 2015 IEEE International Solid-State Circuits Conference – (ISSCC) Digest of Technical Papers, Feb 2015, pp. 13.

10. M. K. Hati and T. K. Bhattacharyya, A pfd and charge pump switching circuit to optimize the output phase noise of the pll in 0.13um cmos, in 2015 International Conference on VLSI Systems, Architecture, Tech- nology and Applications (VLSI-SATA), Jan 2015, pp. 16.

11. S. Jang, S. Kim, S. H. Chu, G. S. Jeong, Y. Kim, and D. K. Jeong, An optimum loop gain tracking all-digital pll using autocorrelation of bang phase-frequency detection, IEEE Transactions on Circuits and Systems Express Briefs, vol. 62, no. 9, 2015, pp. 836840.

12. V. Macaitis and R. Navickas, Cmos technology based lc vco review, in 2015 Open Conference of Electrical, Electronic and Information Sciences (eStream), April 2015, pp. 14.

13. I. K. Saini, T. Singh, and R. Dinesh, An inductor-less lc-vco for ka band using 90nm cmos, in 2015 International Conference on Green Computing and Internet of Things (ICGCIoT), Oct 2015, pp. 534538.

14. W.-S. Chang, P.-C. Huang, and T.-C. Lee, A fractional-n divider-less phase-locked loop with a subsampling phase detector, vol. 49, No. 12, 2014, pp. 29642975,.

15. N. K. AnushKannan, H. Mangalam, V. A. Dharani, G. Divya, N. Esack, and M. Gokulraj, Comparison and analysis of various pfd architecture for a phase locked loop design, in 2013 IEEE International Conference on Computational Intelligence and Computing Research, Dec 2013, pp. 14.

16. M. T. Hsu and P. H. Chen, 5ghz low power cmos lc vco for ieee 802.11a application, in Asia-Pacific Microwave Conference 2011, Dec 2011, pp. 263266.

17. S. Milicevic and L. MacEachern, A phase-frequency detector and a charge pump design for pll applications, in 2008 IEEE International Symposium on Circuits and Systems, May 2008, pp. 15321535.

18. L. Dussopt and G. M. Rebeiz, A low phase noise silicon 18-ghz push- push vco, IEEE Microwave and Wireless Components Letters, vol. 13, no. 1, 2003, pp. 46.

19. G.-C. Hsieh and J. C. Hung, Phase-locked loop techniques. a survey, IEEE Transactions on Industrial Electronics, vol. 43, no. 6, Dec 1996, pp. 609615.