Design and Simulation of Double Precision Floating-Point Adder

Design and Simulation of Double Precision Floating-Point Adder

Sharon Bhatnagar

Student, Department of ECE Lakshmi Narain College of Technology

Bhopal, India

Soheb Munir

Assistant Professor, Department of ECE Lakshmi Narain College of Technology Bhopal, India

AbstractFloating point numbers are very important part of computer processing. Addition imposes a great challenge due to its processing time. This paper presents a technique for addition of IEEE 754 double precision floating-point numbers within two clock cycles. This paper results also show improvements in power utilization, operational chip area management and optimization of hardware. This proposed adder is implemented with the help of 6slx45tfgg484-3 Spartan family as well as 5vfx70tff1136-1 of Virtex Xilinx FPGA devices.

KeywordsIEEE 754,Floating Point Addition,Adder,FPGA

1. INTRODUCTION

   By using floating point numbers in computation we can represent number in a way that it can tradeoff between range as well as precision. As we know computer memory is limited so we cannot store any number with infinite precision so we use floating point numbers. From early times so many formats have been used but since 1990 IEEE make a standard for floating point numbers (IEEE 754).In this there are two kinds of format IEEE 754 single precision and IEEE 754 double precision format. Floating point numbers are represented in the form.

   Sign Bit

   Biased exponent

   Significand/mantissa/fraction

   Sign bit represents the sign of the number if it is zero then it represents a positive number and if it is zero then represents negative number, exponent field determine range of numbers which can be represented, significand represents precision of number.

   PARAMETER	IEEE-754 SINGLE PRECISION	IEEE-754 DOUBLE PRECISION
   Total no. of bits	32	64
   Significand bits	23+1	52+1
   Exponent bits	8	11
   Sign bit	1	1
   Special e value	255	2047
   Bias	127	1023

   Here we concentrate on double precision floating point numbers. Simply if we want to convert a number into IEEE 754 double precision format. First we need to convert that number into binary then it should be normalized and exponent is biased and then written in standard format. Suppose we have number (-3.75). Then binary conversion of 3 is (11) and for 0.75 it is (1011).So (3.75) is equal to (1.11011*2^1), as exponent is one here it must be biased means (1023+1)=1024 it is again converted into binary. The final conversion of (- 3.75) into IEEE 754 double precision format is 1

   10000000000111000000000000000000000000000000000000

   000000000000000.

   Lots of work have been done in this field. First implementation is done by l.louca and T.Cook and W.Johnson in 1996.The algorithm in[2] implement adder, subtractor and multiplier designs and achieved the operating frequencies of 363.76Mhz and 414.714hz with an area of 660 and 648 slices. Error detection technique is presented in [3].Optimization of each individual component of adder has been done in [4].Overall speed is the main concern of the operation due to large number of bits.

   The proposed algorithm is implemented with the help of Xilinx FPGA device 6slx45tfgg484-3 and 5vfx70tff1136- 1.Various parameters like number of slice flip-flops, Number of 4 input LUTs, number of global clks have been observed. Proposed technique show improvements in hardware optimization, latency and chip area compare to algorithm used in [1].

   Rest of the paper is organized as section II presents addition of two floating point numbers. Section III describes the proposed algorithm. Section IV shows the device usage section V shows the simulation results. Section VI contain conclusion and future scope is provided in section VII.

2. ADDITION OF TWO IEEE 754 DOUBLE PRECISION FLOATING POINT NUMBERS

   In order to add to given numbers into double precision the

   two numbers primarily converted into double precision format and the exponents of two numbers are compared if it is equal then we can directly add the numbers and normalize the answer but if the exponent is not equal then we need to rewrite smaller number such that its exponent matches with the larger number and then addition has been performed. After the result of addition it must be normalized.

   difference , then big number is determined out of two exponents by implementing conditions when both the exponents have same sign and both the exponents have different sign. Then greater mantissa is selected for shifting operation and shifting is done for equalization of exponents. All of this operation is done in 1st clock cycle. In next clock cycle two mantissa are added and then normalization has been done.

   IV. IMPLEMENTATION DETAILS

   Somsubhra Ghosh implemented the proposed algorithm with XC2V6000 and XC3S1500 xilinx FPGA devices[1].Similar algorithm when implemented with 6slx45tfgg484-3 improvement in results has been noticed and tabulated as follows.

   Device Utilization Summary
   Logic Utilization	Used	Available	Utilization
   Slice Logic Utilization
   Number of Slice Registers	63	54576	1%
   Number of Slice LUTs	645	27288	2%
   Number used as Logic	645	27288	2%
   Slice Logic Distribution:
   Number of LUT Flip Flop pairs used	645
   Number with an unused Flip Flop	582	645	90%
   Number with an unused LUT	0	645	0%
   Number of fully used LUT-FF pairs	63	645	7%
   IO Utilization
   Number of IOs	193
   Number of bonded IOBs	192	296	64%

   Table1: Estimation of usage of resources in device 6slx45tfgg484-3

3. PROPOSED ALGORITHM

Alignment 1

swapping

Significands complement

Exponent difference

Proposed algorithm is similar to as used in [1].The floating point arithmetic operation uses two clock cycles here. In [1] it is also a two staged pipeline which is divided into two paths. The two paths (R path and N path) are selected on the basis of the exponent difference. The two pipeline stages execute in two different clock cycles. In very first step for this paper, algorithm is written for determining the exponent

flip-flops

Alignment2

———————————————————-

Minimum input arrival time before clock is: 27.424ns Maximum output required time after clock: 5.463ns Maximum combinational path delay: 39.551ns Latency: 2 clock cycles

Table 2: Estimation of usage of resources in device 5vfx70tff136-1

Significand addition

Rounding decision

Post normalization

Normalization alignment

output

RESULT [0, 64]

Table 2 give results of same algorithm on virtex 5.Number of resources are increased from Spartan 6 to virtex 5 and same results are arrived this simply proves that when same algorithm implemented on virtex 2 we get improved results.

1. SIMULATION RESULTS

2. CONCLUSION

The double precision floating point adder is successfully implemented .If the algorithm is implemented on the advanced versions then better results will be derived in future.

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