Design and Synthesis of 32 BIT ALU Using Xilinx ISE V9.1i

Design and Synthesis of 32 BIT ALU Using Xilinx ISE V9.1i

Kaushik Chandra Deva Sarma*, Amlan Deep Borah*, Lalan Kumar Mishra*

*(Department of ECE, Central Institute of Technology, Kokrajhar-783370)

Abstract

The paper presents Design and Synthesis of 32- BIT Arithmetic Logic Unit (ALU). The design has been implemented using VHDL Xilinx Synthesis tool ISE 9.1i and targeted for Spartan device. ALU is designed to perform Arithmetic operations such as addition, subtraction, overflow; logical operations such as AND, OR, XOR, XNOR and NOT operations, Parity check, 1s and 2s complement operations, compare, etc. The ALU is a fundamental building block of the Central Processing Unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and Graphics Processing Units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Flags like Zero, Carry and Odd Parity show the status of each Flag for result of the ALUs operation in each clock cycle. Zero Counter counts number of zeros in the result. The modern ALU must be capable to perform all the binary arithmetic and logical operations to meet the requirements of modern VLSI industry. So, the paper is a forward step to design the ALU and meets the demand of present FPGA based technology. The paper presents a number of new operations (Parity,Overflow,Zero,Zero counter etc.) that an ALU can perform than so far designed ALU in VHDL.

Keywords: 32 BIT ALU, VHDL,Network Interface Card, Processor

1. INTRODUCTION

   Design of ALU in VHDL has been more complex to meet the requirements in terms of number of operations and fast operation and so it has been more efficient over the years. The number of operations performed by an ALU has been consistently increasing. ALU is a core component of all Processor and is an Integral

   part of the execution unit. The ALU performs the decision making operations (logical) and arithmetic operations. Arithmetic operations involve functions such as addition, subtraction, There are a variety of techniques to design these functions. It is most complex with regard to design, amongst all the components of the computer, and it also contributes to most of the delay. Thus, the design of the ALU is critical to the speed of the computer. The ALU can efficiently perform parity check to utilize it in Digital Systems. The faster adder can perform fast addition operation. The ALU is used in Network Interface Card (NIC) to maximize the throughput.

2. 32 BIT ARITHMETIC AND LOGIC UNIT

The 32 BIT ALU can perform advantageous Flag operations e.g. Parity, Carry, Overflow. The Flags play crucial role in Digital System Design. The 32 BIT ALU can perform advantageous Flag operations e.g. Parity, Carry, Overflow. The Flags play crucial role in Digital System Design. Parity Flag can detect the error and thus be used in Digital communication.

Fig.2.1: Entity 32 bit ALU

Design of Microprocessor through VHDL is importantly dependent over the efficiency of ALU design and synthesis. The less the delay propagation the more ALU is efficient to speed up digital signal operation. Software-based Programmable Network Interfaces excel in their ability to implement various services. These services can be added or removed in the network interface simply by upgrading the code in the system. However, programmable network interfaces suffer from instruction processing overhead. Programmable NICs must spend time executing instructions to run their software whereas ASIC based network interfaces implement their functions directly in hardware.

i). Design of Arithmetic Block:

The ALU can perform 32 BIT Addition and Subtraction operation and Overflow Logic will be HIGH if the result exceeds 32 BIT. Full Adders and Full Subtractor have been designed using Carry Ripple adder concept. Carry Flag show the result status whether output contains carry or not. Overflow Flag will be HIGH when 31st carry and 32nd bit of carry gets HIGH upon XOR operation. Zero Counter counts number of Zeros in the result (i.e. Outr).

ii).Design of Logic Block:

The Logic Block can perform all logical operations e.g.

XOR,XNOR,NOR,NAND,AND,NOT,OR etc

and generates Flags e.g. Parity, Carry, Zero if required.

iii).Design of Comparator

The ALU compares upon the two inputs and results either Ain>Bin, Ain<Bin or Ain=Bin. The Select Line (4 BIT) decides which operation is to be performed by the ALU e.g. XOR, NOR,NAND ,Addition, Subtraction etc. The Flags e.g. Parity, Zero etc are independent of Select Line. So, Flags will be HIGH or LOW in each clock cycle.

III. Table I

Select Line	Operation
0000	Ain AND Bin
0001	Ain OR Bin
0010	Ain AND (NOT Bin)
0011	Ain XNOR Bin
0100	NOT Bin
0101	Ain NAND Bin
0110	Ain NOR Bin
0111	XNOR
1000	NOT(Ain XNOR Bin)
1001	NOT(Ain NAND Bin)
1010	NOT (Ain NOR Bin)
1011	Carry Ripple Adder, Carry, Overflow
1100	Carry Ripple Subtractor, Carry, Overflow
1101	32bit Adder
1110	32bit Subtractor
1111	Ain NOR (NOT Bin)

Fig.2.2RTL Schematic

1. Simulation:

   Simulation of Behavioral Model for 32 BIT ALU has been performed for 1000 nano-seconds. Each Clock(CLK) cycle has 50 ns rise and fall time. Input Setup time:5 ns, Output Valid delay:3 ns;

   The simulation of 32-BIT ALU(if rising_edge(CLK) and EN=0) generated from Testbench Waveform is given in figure 2.1 below:

   Fig.2. Testbench Simulation

2. Synthesis and Implementation Report (XILINX ISE v9.1i):

   The Synthesis and Implimentation Reports have been generated by XILINX ISE v9.1i for the Behavioral model of 32 BIT ALU are given below:

   1. Advanced HDL Synthesis:

      —————————————————

      Macro Statistics

      # Adders/Subtractors: 35

      1. bit adder carry out 1

      2. bit adder 1

      1. bit adder carry out 1

      2. bit adder 3

      3-bit adder carry out 1

      1. bit adder 1

      2. bit adder 1

      33-bit adder carry in 1

      33-bit subtractor 1

      4-bit adder 7

      1. bit adder carry out 1

      2. bit adder 15

      5-bit adder carry out 1

      # Registers: 44 Flip-Flops	: 44	Minimum input arrival time before clock: 62.522ns
      # Comparators	: 2	Maximum output required time after clock:
      32-bit comparator greater	: 1	12.314ns
      32-bit comparator less	: 1	———————*****——————————
      # Multiplexers 3 1-bit 16-to-1 multiplexer	: 2	3.3 The Dela Summary Report:
      32-bit 16-to-1 multiplexer	: 1	——————————————————-

      # Xors 38

      1-bit xor2 3

      1-bit xor3 33

      1-bit xor32 1

      32-bit xor2 1

      ————————*******————————

   2. Timing Summary:

——————————————————-

Speed Grade: -4

Minimum period: 2.377ns (Maximum Frequency: 420.698MHz)

The NUMBER OF SIGNALS NOT

COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for

this design is: 3.480 nano-seconds

The MAXIMUM PIN DELAY IS:

11.932 nano-seconds

The AVERAGE CONNECTION DELAY on

the 10 WORST NETS is: 7.830 nano-seconds

——————–*****——————————

Fig.3. Design Utilization Summary Conclusion:

The paper Design and Synthesis of 32 BIT ALU using Xilinx ISE Design Suite v9.1i we have designed and implemented a 32 bit ALU. Arithmetic Logic Unit is a part of digital system that performs arithmetic computations, such as Addition and Subtraction, Parity, Comparator, Overflow and all sorts of basic logical operations(NAND,NOR,XOR,AND,OR). The ALU is one component of the CPU (Central Processing Unit) and used in various work. Here all the above mentioned operations are then

verified by Xilinx IES Design Suitev9.1i to see whether they match theoretically or not. The above given waveforms show that they match completely thereby verifying our results.

Acknowledgement

It is our immense pleasure to find an opportunity to express our deep gratitude and sincerest thank to Asst. Prof. Arindum Mukharjee (CIT, Kokrajhar) and Asst. Prof. Rajib Chetia (CIT, Kokrajhar) for giving most valuable suggestion, helpful guidance and encouragement in completion of our project and providing us all

possible assistance. They have been extremely motivating and helped during the execution of this project work that has led us to the successful completion of our project titled: Design and Synthesis of a 32-bit ALU on Xilinx ISE v9.1i using VHDL. We highly appreciate the efforts and numerous suggestions that they structured our work with their valuable tips and accorded to us in every respect of our work. At last, we humbly extend our sincere appreciation to other faculty also who help and encouraged us in some way or during our working project environment.

References: Journal:

[1] Suchita Kamble1, Prof .N. N. Mhala VHDL Implementation of 8-Bit ALU, IOSR Journal of Electronics and Communication Engineering (IOSRJECE) ISSN : 2278-2834 Volume 1, Issue 1 (May-June 2012) [2]Geetanjali and Nishant Tripathi. VHDL Implementation of 32-Bit Arithmetic

Logic Unit (Alu),International Journal of Computer Science and Communication Engineering, IJCSCE Special issue on Emerging Trends in Engineering ICETIE 2012

[3]Rupali Jarwal and Ulka Khire,4-Bit Arithmetic And Logic Unit Design Using Structural Modelling In VHDLInternational Journal of Engineering Research & Technology (IJERT),Vol. 2 Issue 3, March – 2013

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