Design of 6T- SRAM Cell Using Dual Threshold Voltage Transistor

Design of 6T- SRAM Cell Using Dual Threshold Voltage Transistor

Presented by Under the guidance of

Chetna Mr. Abhijeet

M-Tech Electronics and Comm. Lect.in Electronics and Comm.

M.M. Engineering College M.M. Engineering College

Maharishi Markandeshwar University Maharishi Markandeshwar University Mullana (Ambala) India Mullana (Ambala) India

Abstract

Most microprocessors use large on-chip SRAM caches to bridge he performance gap between the processor and the main me mory. Due to their growing embedded applications coupled with the technology scaling challenges, considerable attention is given to the design of low-power and high-performance SRAMs. Static random access me mories (SRAM) are widely used in computer systems and lots of portable devices. In this paper, we proposed 6T-SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit lines while high threshold volt – age transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain d ata retention at the same time.

Hence, high-speed and low-power 6T-SRAM cell operations of the SRAMs are feasible. This paper presents a 5-transistor dual voltage SRAM cell intended for the advanced microprocessor cache market using 1.8v/0.18um cmos technology. The goal is to reduce the power of the cache memory array while maintaining competitive performance

1. Introduction

   Se miconductor me mories are most important subsystem of modern digita l systems. In new era the scaling of silicon technology has been ongoing, due to scaling large

   me mo ry can be fabricated on a single chip as results me mo ries are capable to store and retrieve large amount of information at high speed. But due to high density, power dissipiation gets increases and speed decreases. So there is need for the design of low power and high speed circuit in me mory. A me mo ry in terms of co mputer hardware is a storage unit. There are many d ifferent types of hardware used for storage, such as magnetic hard drives and tapes, optical discs such as CDs and DVDs, and electronic me mo ry in form of integrated me mory or stand-alone chips.[6]

   The ma in focus of this paper is the SRAM. There are some very important require ments for a me mory when it is to be embedded as on-chip cache. First and foremost it has to be reliable and stable. This is of course true for all me mo ries, but is especially important for cache due to the more e xt re me performance require ments and area limitat ions. Secondly the me mory has to have high performance. The sole purpose of cache is to speed up the operation of the CPU by bridging over the performance gap between main me mory and the CPU. Another

   most important require ment is low power consumption. Todays advanced mic roprocessors use a lot of power and get very hot as a result. With increasing me mory sizes these contribute with more and more power loss. This is especially important in mobile applicat ions where

   prolonging battery life strongly depend on minimizing power loss.

2. Proble m associated with single vth SRAM cell

   There are many techniques which reduces power dissipiation and wake lo w power SRAM ce ll d ivided word line architecture, me mory banking architecture,

   pulsed world line and reduced voltage swing techniques

   be reduced, which will in turns shorten the access time of the 6T- SRAM cell

   WL = Vcc

   M5 Vdd M6

   Vthp Vthp

   are used to reduce only active power dissipitation. On the other hand during standby mode, there is leakage power disspitation due to presence of sub threshold and gate

   M3 w = 1.08

   L = 0.18

   w = 0.40

   L = 0.18

   Node1

   w = 0.28

   w = 0.36

   L = 0.30

   Node2

   w = 0.40

   w = 0.45

   L = 0.18

   M4

   tunneling leakage currents

   M1 L = 0.18

   L = 0.18 M2

   Vthn Vthn

   WL = Vcc

   M5 Vdd M6

   BL BL

   Figure-2 Schematic of Dual Vth 6 -SR AM Cell with Final Sizes [1]

   Node1

   M3

   Node2

   M4

   Hence we use the low-Vth transistors to imp le ment the driving transistors. It will produce a la rge driv ing current

   M1 M2

   BL BL

   Figure-1 Subthreshold and Tunneling Gate Leakage of SRAM Circuit [2]

   To avoid these leakage, Dua l therehold (dual Vth) techniques applied on Conventional SRAM ce ll.

3. Dual vth 6T SRAM cell

   A typical dual Vth 6T -Ce ll is shown in fig-4.3. The access transistors M3 and M6 a re controlled by the world line (WL).It threshold voltage of N3 and N4 is lo w , the switching time of N3 and N4 will be reduced, wh ich will

   than normal or h igh-vth transistors By contrast, transistors with high Vth possess low lea kage current and sub threshold current. Thus, they are very good to be cross coupled as a data latch. Thick channel transistors are showing high threshold voltage (high Vth), while thin channel transistors are showing low threshold voltage (low Vth) in fig shown below. [7]

   Design of 6T -SRAM Ce ll is started with ma king Schemat ic after that optimizat ion of 6T-SRAM Ce ll is done is done in such a way that it meets the required objectives. Write operation is possible for dual Vth 6T- SRAM ce ll with transistors sized for a 0.18u m CM OS technology for p roper write operation simulat ions are done for different width of transistor. The simulat ion results show a significant a mount of average power reduction.

   Figure-3 Voltage waveforms of Dual Vth 6T-SRAM

4. Simulation wave forms of dual Vth 6T- SRAM cell

Non-distractive write operation is possible for dual Vth 6T-SRAM cell with t ransistors sized for a 0.18u m CM OS technology for p roper write operation simulat ions are done for different width of transistor. The width is varied in steps of 0.04 u m. The results of these simulations are shown in fig-4.

Figure-4 Simulation wave forms of dual vth 6T-SRAM

The simu lation results show a significant a mount of average power reduction by Dual – Vth 6T-SRAM Cell.

4. Conclusion

In this paper, the analysis and simulation is done for Dual

– Vth 5T- SRAM Ce ll as co mpared with Dual – Vth 6T- SRAM Ce ll using 1.8v/0.18u m c mos technology. The values of sensing delays and average power consumption are calculated fo r diffe rent sizes of CMOS-Transistors.

Table-1 Write delay in dual vth 6T-SR AM Cell

Table-2 Write power consumption in dual Vth 6T-SRAM

Hence all of these parameters have adjusted together until a satisfactory result is achieved. For instance sizing of transistors have been done in such a way that 6T-SRAM

cell can reduce power consumptions and delay shown in above tables.

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