Design of a 2.4 GHz Common Source LNA with Inductive Degeneration for RF-IC

Design of a 2.4 GHz Common Source LNA with Inductive Degeneration for RF-IC

Laxmi Gupta

Electronics and Communication Department Jaypee Institute of Information Technology Noida, Uttar Pradesh, India

Abstract This paper illustrates a 2.4 GHz low noise amplifi- er (LNA) designed for use in RF receiver system for radio frequency integrated circuit (RFIC). The design has been made in 90 nm technology using CMOS. The proposed LNA design uses common source configuration with inductive de- generation technique. This technique provide high linearity The simulation result shows that total power consumed is 15.6mW only at low supply voltage of 1.5 V. This amplifier provides a forward gain of with a low noise figure of 0.58dB. The input return loss (S11) is -9.6dB and output re- turnloss (S22) is -2.2dBrespectively. This amplifier provides a forward gain of 11dB at 2.4 GHz.

Keywords Low noise amplifier(LNA), Noise Figure (NF), Gain, RF

Ankita Bharti

Electronics and communication Department Jaypee Institute of Information Technology Noida, Uttar Pradesh, India

with the standard, which includes low power and low data rate. So, the design of LNA is aimed at lower power con- sumption We try to make LNA such that it provide a min- imum noise figure while providing sufficient linearity with gain and a stable 50 resistance for the impedance match- ing. Impedance matching play significant role and it is crit- ical when a preselect filter such a BPF precedes the LNA in RF receiver system.

1. INTRODUCTION

   Wireless sensor network is emerging as a popular recent trend in new markets. Radio frequency (RF) is an electro- magnetic wave frequency whose range is around 3KHz to 300GHz. As shown in block diagram of RF receiver sys- tem signal coming from antenna is RF signal. RF receiver is used in two way devices such as radios and mobile phones etc. Wireless local area network (WLAN) at 2.4 GHz is emerging very rapidly. CMOS is having advantage of ease of integration. It can be scaled to any technology and hence due to higher level of integration, it reduces cost of wireless communication systems[2]. RF receiver is battery powered [1]. Power consumption can be reduced by

   adequate receiver sensitivity. This can be done using low noise amplifier (LNA). LNA is a first building block of wireless network. It affects the performa-nce of re- ceiver of RF receiver system. It consumes less chip area because it uses MOS devices which is active component when implemented on chip uses less area as compared to lumped components (R,L,C). It also consumes less power, less noise, high linearity and adequate gain [2]. The basic block diagram of RF-receiver is shown in fig (1). The overall performance of the RF receiver system depends on the LNA gain and noise figure(NF). The LNA design faces several challenge Such as such as sufficient gain to sup- press noise, low power, high linearity low noise figure and impedance matching because every communication sys- tems implementation with

   Fig (1). Block diagram of RF receiver system

   This paper includes the design and implementation of Low Noise Amplifier in 90nm technology. This paper is orga- nized in following manner; Section II gives proposed LNA design. Section III gives simulation result and section IV is the conclusion of our paper.

2. LNA CIRCUIT DESIGN

   1. opologies Used In Lna Design

      LNA circuit should be simplified as much as possible be- cause if it is complicated then parasitic effects are intro- duced. So different topologies are introduced for single ended narrow band low power, low voltage design, low noise figure such as common source with resistor, common gate, common source with shunt series feedback, cascode inductive degeneration source and inductive degeneration common source respectively and these types of topologies are shown in Fig (2). But in proposed design of LNA we have used common source with inductive degeneration type of topology is shown in Fig (3).

      Value of Cgs, Cex, Ls, F0 is calculated by given equa- tions,and gain(Av) is calculated by the formula given be- low:

      1. (b)

   Av = /

   (7)

   (c) (d)

   Fig.2. LNA Architectures (a) Resistance Match (b) Feedback Structure (c) Common Gate Structure (d) Inductive Degeneration

   This LNA design approach uses common source with in- ductive degeneration type of topology to provide high line- arity [5]. This LNA operates at 1.5 V of power supply. The matching provided at input and output port is 50. Match- ing network consist C1 and C2 and small inductor. Thumb

   Fig 3 Circuit layout of proposed design

3. DESIGN SPECIFICATION

   The sensitivity of communications system is limited by noise. The noise factor (F) of a system is defined as:

   rule says that if Ibias= 1mA than the value of gm will be 10 to 20 times the value of Ibias. For this circuit value of Ibias is 10mA, if this device works in weak inversion region than

   F SNRi 1 Na

   SNRo Ni

   (8)

   to maintain linearity it is quite difficult so the device should operate in saturation region. According to the rule if the device is operated at certain current of any value than you should maintain the overdrive voltage Vdsat at 200mV. It means the device is working in strong inversion, if Vdsat

   Where: (SNR)I and (SNR)o are the signal to noise ratios in the input and output ports respectively. The Ni is the noise present at input source and the Na is the overall noise due to circuit. The Noise Factor of a series system is given as:

   goes below than gm goes high for same Ibias. The relation

   F F F 2 1 F 3 1 ………………….

   (9)

   between Vdsat and

   is given by formula which is define

   total

   1 G1

   G1G2

   below. The total capacitance offered by gate and drain terminal is given as:

   where F1, F2, F3, G1, G2, G3 are the noise factors and power gains at each stage of the design.

   2L

   I d n C ox W (V gs V t)2

   (1)

   Eqn.(9) Shows that if the power gain of the first stage is

   V

   2

   dsat

   2I

   '(W )

   (2)

   large then the total noise factor will be dominated by the first stage of the design. Since LNA is the first basic block

   k n L

   Cgs=Cox× × (3)

   Cex= Cgs+2ds (4)

   in the receiver path, so LNA should provide enough gain and generate noise as less as possible.

4. SIMULATION RESULTS

   Z= gm×

   F0= 1

   2(+ )

   (5)

   (6)

   This section describes simulated results of common source with inductive degeneration technique operated at 2.4 GHz. The design was simulated using 90nm technology. These are the figures (4-7) represents the S-parameter curves, from the simulation results it is shown that input signal fre- quency varying from 1GHz. This shows that S11 (input re- flection coefficient), S12 (reverse gain coefficient), S21 (forward gain coefficient), S22 (output reflection coeffi- cient) respectively.

   With the help of S-parameter we can calculate the insertion and return losses. The input return loss (S11) is – 9.6dB and the output return loss (S22) is -2.2dB. The max- imum power gain (S21) is 11dB at 2.4GHz. The S12 is – 16dB. The circuit is designed to achieve the target 2.4 GHz.

   Fig 4 Simulation result of Input reflection coefficient S11

   Fig 5 Simulation result of reverse gain coefficient S12

   Fig 6 Simulation result of forward error coefficient S21

   Fig 7 Simulation result of output refection coefficient S22

   <>All the on chip inductors used here are spiral in nature. All the on chip capacitors here are MIM (Metal-Insulator- Metal) capacitors. The parasitic effects of MOSFET have also been considered. When the transistors have been seized it provides good noise characteristics, while allow- ing a good input impedance matching over the targeted fre- quency. The measured noise figure is shown in fig(8).

   Fig(8) Simulation result of Noise Figure

   TABLE: (1) COMPARISON BETWEEN 2.4GHz CMOS LNAs

   References	[1]	[4]	[6]	[7]	[10]	This Work
   Technolo- gy(um)	0.13u m	0.13u m	0.18u m	0.13u m	0.18u m	0.09 um
   Supply Volt- age(V)	1.2	0.8	1.8	0.6	1.0	1.5
   Frequen- cy(GHz)	2.4	2.4	2.4	2.4	2.4	2.4
   Gain(dB)	20.0	22.0	13.7	14	12.92	11.0
   S11,S22(dB)	NA	NA	NA	NA	NA	-9.6, -2.2
   NF(dB)	4.0	3.6	2.77	3.8	3.8	0.58
   Power(mW)	1.32	0.8	18	0.12	13	15.6

   Table:1 describes the performance of this proposed LNA and compare it with other published circuit performance. Our proposed LNA achieves low power consumption and noise figure at 90nm technology.

5. CONCLUSION

The proposed design of LNA in this paper is implemented in 90nm technology. This paper describes a new topology of LNA , we have chosen the inductive degeneration topol- ogy in this LNA design which offers a low noise figure 0.58dB and high linearity under 1.5V power supply volt- age. The simulation results have shown that the proposed LNA consumes only 15.6mW power while achieving a power gain of 11dB. This proposed design of LNA has rel- atively small noise figure and power consumption at 90nm technology. This LNA also works in the ISM band applica- tion. The simulation results validate peak performance at 2.4GHz that suitable for wireless sensor network.

ACKNOWLEDGEMENT

The authors are grateful to Jaypee Institute Of Information Technology for providing resources at the department of Electronic and communication Engineering to enable them to carry out this research work.

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