Design of A Reconfigurable Architecture for 1-D DWT using Pipeline Architecture

Design of A Reconfigurable Architecture for 1-D DWT using Pipeline Architecture

1Vimala M. S

14th sem, M.Tech (VLSI & Embedded System)

SSIT, Tumkur

2Savitha C 2Assistant professor, Dept. of ECE,

SSIT, Tumkur, Karnataka

3Dr. M. Z Kurian 3HOD, Dept. of ECE, SSIT, Tumkur

ABSTACT-In this novel, the proposed reconfigurable architecture is designed by using lifting method instead of convolution method. Lifting method reduces considerable hardware and computational complexity where hardware resources are major components of DWT. The reconfigurable architecture is classified into two modes for throughput and different bandwidth respectively.

Keywords: DWT; Pipeline architecture

1. INTRODUCTION

   Wavelet transform is introduced by Mallat where decomposition of samples into basic functions called wavelets on the orthogonal basis[1]. Thus, DWT does not contain any redundant data after transformation. Therefore, it leads to high compression ratio.

   The DWT computation is classified into two methods i.e. convolution and lifting methods. The convolution method has better scalability and regularity. The advantages of lifting method are, 1. Lifting increase considerable speed when compared other standard design.

2. Lifting supports an in-place implementation of the fast wavelet transform, which is similar to the Fast Fourier Transform. Therefore, wavelet transform can be calculated without allocating auxiliary memory. 3. All operations within one lifting step can be done entirely parallel while the only sequential part is the order of the lifting operations. 4. Non linear wavelet transforms can easily build by using lifting method.5. Using lifting and integer- to-integer transforms, it is possible to combine bi- orthogonal wavelets with scalar quantization and still keep cubic quantization cells which are optimal like in the orthogonal case.

The lifting based pipelined architecture has lower hardware complexity and higher throughput for computation.

2. LIFTING METHOD

The main feature of the lifting-based discrete wavelet transform scheme is to break up the high-pass and

low-pass wavelet filters into a sequence of smaller filters that in turn can be converted into a sequence of upper and lower triangular matrices [4]. The basic idea behind the lifting scheme is to use data correlation to remove the redundancy. The lifting algorithm can be computed in three main phases, namely: the split phase, the predict phase and the update phase, as illustrated in Fig.1.

Fig.1: Split, predict and update phases of the lifting based DWT

Split phase, In this split phase, the data set x(n) is split into two subsets to separate the even samples from the odd ones:

Xe = X(2n), Xo= X(2n+1) (1)

Prediction phase, In the prediction stage, the main step is to eliminate redundancy left and give a more compact data representation. At this point, we will use the even subset x(2n) to predict the odd subset x(2n+1) using a prediction function P. The difference between the predicted value of the subset and the original value is processed and replaces this latter:

Y(2n+1) = Xo(2n+1) P(Xe) (2)

Update phase, The third stage of the lifting scheme introduces the update phase. In this stage the coefficient x(2n) is lifted with the help of the neighboring wavelet coefficients. This phase is referred as the primal lifting phase or update phase:

Y(2n) = Y(2n+1) + U(Xe) (3)

Where, U is the new update operator.

Fig.2: Pipelined architecture for 1-D DWT.

The 1-D pipelined architecture is designed by using 6 multiplier, 8 adders and 14 registers which is as shown in fig.2. The pipeline registers depends on their relative position. The registers located before alpha multiplication in the odd dataflow and before beta multiplication in the even dataflow store integers from -127 to 128. The registers located after beta multiplication in the odd dataflow and before gamma multiplication in the even dataflow store integers from -184 to 184. The registers located after gamma multiplication in the odd dataflow and before delta multiplication in the even dataflow store integers from -205 to 205. The registers located after delta multiplication in the odd dataflow and before division by k store integers from -366 to 366. The register located at output data of the even dataflow corresponds to low frequency of input image samples store values from -298 to

1. The register located at output data of the odd dataflow corresponds to high frequency of input image samples store values from -252 to 252. These 9 bits, even though a low magnitude value is expected for this data output due to the nature of the transform of still tone images[4].

   1. RECONFIGURABLE ARCHITECTURE

      Fig.3: Reconfigurable Block constructed by 4 CUs.

      A single reconfigurable block is constructed by 4 CUs, because the optimal number of CUs for processing 2-D DWT is 4[6]. The control logic controls the data flow between the external memory and the reconfigurable blocks.

      The multiplexers MUX0 and MUX1 change the interconnections among CUs to reconstruct the computing circuit into different structures.

      Each computing unit consist of local memory at the beginning and FIFO at the output stages respectively and MLBF(MAC loop based filter).

      Fig.4: Reconfigurable architecture for MODE1.

      In MODE1(cooperation among multiple CUs), all four CUs of reconfigurable block work on same decomposition level in parallel is as shown in Fig.3, Where high throughput is the major concern of the task and the bandwidth of the EX MEM is sufficient[4].

      Fig.5: Reconfigurable architecture for MODE2.

      In MODE 2(multi-level 1-D DWT), the circuit is considered as 3-level structure is as shown in Fig.4. The first level is composed of 2 CUs, which are CU00 and CU10, the second and the third level are separately built by CU01 and CU11. Since the number of operations of the second level is only half of the first level, the hardware resource required by the second level is also half of the first level. The efficiency of the CU11 is reduced to half by cascading CUs[3].

   2. PROPOSED DESIGN

      The same reconfigurable architecture with small change is considered i.e. Local memories at each computing units are suppressed. The input to the CUs is taken directly from the external memory.

      Therefore, the memory size required is reduced compared to reference paper. Thus, it increases throughput and also by using pipeline architecture the hardware resources are also reduced.

      4.1 FILTER COEFFICIENT

      Coefficients	VALUE	BBRF
      	1.58613	1.100110
      	0.05298	0.00010010
      	0.88291	0.11100000
      	0.0.443506	0.100100010
      	0.81289	0.11100010
      1/	1.152344	1.010110010

      Table.1: Coefficient for Pipelined Architecture

   3. SIMULATION RESULTS

      1. PIPELINED ARCHITECTURE

         Fig.6: RTL schematic

         Fig.7: ISIM simulation results

         Fig.8: Design Summary

      2. RECONFIGURABLE ARCHITECTURE

      Fig.9: RTL schematic

      Fig.10: ISIM simulation results for MODE1

      Fig.11: ISIM simulation results for MODE2

      Fig.12: Design Summary

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   4. CONCLUSION

The proposed design requires less hardware resources and increased the throughput and decreases bandwidth in MODE1 and MODE2, respectively.

Therefore, it consumes less power than the previous work.

REFERENCES

1. S. G. Mallat, A theory for multi-resolution signal decomposition: the wavelet representation, Pattern Analysis and Machine Intelligence, IEEE Transactions on, vol.11, pp.674-693,1989, doi: 10.1109/34.192463

2. M. Vishwanath, The recursive pyramid algorithm for the discrete wavelet transform, Signal Processing, IEEE Transactions on, vol.42,pp.673-676,1994,doi10.1109/78.277863

3. Qing Sun, Jiang Jiang, Yongxin Zhu, Yuzhuo Fu., A Reconfigurable Architecture for 1-D and 2-D DWT, Field Programmable custom computing machines, 21st Annual International IEEE Symposium on 978-0-7695-9/13, doi: 10.1109/FCCM.2013.23