Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications

Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications

Prema Kumar. G Shravan Kudikala

Casest, School Of Physics Casest, School Of Physics

University Of Hyderabad University Of Hyderabad Hyderabad, India Hyderabad, India

Abstract: This paper presents the detailed design of Miller compensated two stage operational amplifier for data converter applications such as Delta-sigma (-) analog-to-digital converters. The op-amp is designed to meet the requirement of high-speed high-resolution Delta-sigma (-) modulators at the cost of moderate power consumption. The circuit is implemented in a TSMC 0.18µm 3.3V CMOS technology. The design is carried out using LTSPICE tool.

Keywords: CMOS operational amplifier, Delta-sigma (-) analog to digital converter, loop filter, stable trans- conductance biasing.

1. INTRODUCTION

   CMOS Operational amplifier is a fundamental building block for numerous analog circuit designs. Operational amplifiers are one of the basic and important circuits which have a wide application in several analog circuits such as delta-sigma (-) analog to digital converters, switched capacitor filters and sample and hold amplifiers etc.The loop filter in delta-sigma (-) analog to digital converters is analog one and can be implemented either in a continuous time (Active-RC filter)or in a discrete-time(switched capacitor filter) active form and they can be implemented using two stage op amp or folded cascode operational amplifiers [1].CMOS two stage op amp best choice for implementation of summing amplifier or loop filter in delta sigma modulators since op amp provides high mid band DC gain, high band width, and high linearity [2].

   The speed and settling accuracy of the delta sigma modulators are determined by the performance of the operational amplifier. The adequate speed of the – modulator is determined by the unity gain frequency and settling time while the settling accuracy is determined by the DC gain of the op amp. In Switched-capacitor circuits charge being transferred from one capacitor to another rapidly in each clock of operation therefore op amp slew-rate limit has to be taken into another design consideration. The Slew rate and bandwidth limitations produce harmonic distortion reducing the total SNDR of the sigma-delta modulators. In typical switched capacitors, the unity gain bandwidth of the operational a general rule of thumb is that the clock frequency should be 5 times than the unity gain frequency and the phase margin is at greater than 70 degrees to ensure stability. In other words the time constant of the filter should be kept smaller

   than the sampling period T, for the modulator to be stable. Further input-referred offset voltage of an op-amp in a CMOS technology typically around 5mV, which becomes more pronounced in low-voltage applications, where the inherent signal swing is reduced.

   This paper describes the design of miller compensated two stage operational amplifier operating at 3.3V for the continuous time delta sigma modulator applications. The design mainly focussed to achieve sufficient electrical characteristics such as unity gain frequency, slew rate, Input common mode range, output swing and output offset all are taken into consideration as power consumption is secondary concern.

2. CIRCUIT DIAGRAM

   1. Topology

      Fig.1 Miller compensated two stage operational amplifier.

      The miller compensated two stage op amp with robust biasing circuit is shown in Fig. 1. It consists of stable trans- conductance biasing circuit and two stage op amp. The first stage usually consists of high gain, differential amplifier. The common source amplifier usually meets the specification of the second stage, having a moderate gain.

   2. Design Specifications

   TABLE I

   I5 = S. R Cc = 50 * 106 * 2.3 * 1012

   = 115 µA

   SPECIFICATIONS

   STEP 3: Assuming the GB established by the dominant node, we have

   Name of the Parameter	Specification
   Power supply	± 1.65 V
   Technology	0.18 µm TSMC
   Open loop gain (Av)	> 70dB
   Gain Band width product (GB)	100MHz
   Phase Margin (P.M)	60 degrees
   Output offset voltage	< 5mV
   Slew rate	50 V/ µ
   Output Voltage Range	2Vpp
   Input common mode range (ICMR)	– 0.8 to 1.3V
   Load Capacitance	10 pF
   Total Power consumption	Minimum

   gm1 = GB * Cc = 2 * * f * Cc gm1 = 120 * 106 * 2.3 * 1012

   = 0.0017 = 1.7 m -1

   W

   = (gm ,1)2

   L 1,2

   =

   Kn I5

   (1.7 103)2

   343 .2 106115 106

   STEP 4: Design for W

   L

   3,4

   = 73.22

   from the maximum input

3. DESIGN CALCULATIONS

   voltage specification.

   This section presents a design procedure for a basic miller compensated two stage CMOS op amp with basic op amp equations.

   W

   L

   W

   3,4

   = I5

   Kp VDD Vin max Vtp ,3 max +Vtn ,1 (min ) 2

   = 115 106

   Basic op amp Equations:

   The following equations are the MOSFET, strong inversion, square law equations:

   L 3,4

   70.4 106 1.651.30.42+0.42) 2

   = 14

   Drain current I = V

   2 = µn ,p COX W V

   2 (3.1) W

   D OV

   2 L OV

   STEP 5: Design for L 5 from the minimum input voltage. First we

   where =µn ,p COX W

   have to calculate V (sat) then find S5.

   2 L

   W 2ID

   DS 5

   VDS 5 = Vin min – VSS – I5 – Vtn ,1 (max)

   1

   Aspect ratio

   L = µ C V 2 (3.2)

   = – 0.8 (-1.65) –

   n ,p OX OV

   115 106

   343.2 106 73 .22

   – 0.57

   Transconductance,

   = 2 µ

   2

   (3.3)

   = 2

   ,

   (3.4)

   = 0.1867

   Where

   = (VGS

   -Vtn

   ) for NMOS and VOV

   = (VSG

   – Vtp

   ) for

   W

   L 5

   2I5

   =

   Kn COX VDS 52

   2115 106

   =

   343.2 106 (0.1867 )2

   = 19.22

   PMOS, will be used throughout the paper. Strong inversion typically requires values of VOV greater than approximately 200mV for bulk MOSFETs room temperature [3].

   STEP 1: Design the compensation capacitor Cc in such a way that placing the pole P2 , 2.2 times higher than the Gain bandwidth product (GB) permitted a 600 phase margin. This results in the following requirement for the minimum value for Cc .

   c L

   C > 2.2 C

   10

   c

   C > 2.2 10 1012

   10

   12

   STEP 6: Find gm6 , gm4 to design W

   L

   6

   For required Phase margin

   gm6 = 10 gm1

   = 10 * 1.7 * 103

   = 17 m -1

   m 3 L 3

   2Kp W I5

   g = 2

   = 270.4 10614115 106

   2

   Cc > 2.2 10

   Choose Cc=2.3pF

   STEP 2: The next step of the design is the estimation of the bias current. From the slew rate specification, we have

   Let VSG ,4 = VSG ,6

   = 0.337 m -1

   Therefore, W = W * gm ,6

   L 6 L 4

   gm ,4

   Slew rate (SR) = ISS

   Cc

   = I5

   Cc

   = 14 * 17 103

   3

   0.337 10

   Where ISS (=I5) is the tail current.

   = 706.23

   Since

   =

   ,

   STEP 7: Calculate I6 flowing through M6

   I = (gm ,6)2

   6 2 Kp W

   There fore , = , .

   Neglecting body effect,

   L 6

   (17 103)2

   we have

   , –

   , =

   = 2 70.4 106706 .23

   ,

   = 2.9 mA

   From the above equation it is observed that

   STEP 8: Design W

   L 7

   to achieve the desired current ratios between

   &

   should not have same value.

   I6 and I5

   W

   L 7

   = W

   L 5

   * I6

   I5

   2.9 103

   For a special case,

   = 4 * W

   L

   M17

   = 19.22 * 115 106

   = 484.67

   STEP 9: Design W by relationship relating to load, compensation

   Re-arranging the above equation

   2 W

   1 L

   M 17 = R

   L 8 2 I

   capacitors, and W

   L 6

   D ,M 16

   µn Cox

   W

   L M 17

   W

   L M 16

   W =

   W

   L

   6

   = 706 .23

   = 132

   Recalling Trans-conductance,

   L 8 C L

   10 W

   1+C c

   1+

   .

   gm,M17 = 2 Kn L

   M17

   ID,M16

4. STABLE TRANSCONDUCTANCE BIASING

   Therefore, gm,M17 = 2

   W

   W

   R

   1 L M 17

   R

   gm ,M17 = 1

   L M 16

   gm,M17 Depends on R, Changing R value gives required bias current.

   Since the aspect ratios for the transistors in the biasing circuit shown in Fig. 3.5 are as follows.

   W

   L

   M12

   = W

   L

   M13

   = W

   L

   M14

   = W

   L

   M15

   and

   Fig. 2. Stable Trans-conductance biasing [4]

   W

   L

   M16

   = 4 * W

   L

   M17

   The bias circuit shown in Fig. 2 is used to stabilize the transistor trans-conductance of the op amp since it supplies constant bias current to the op amp. Biasing circuit is independent of power supply voltage variations.

   Writing KVL to the loop as shown in Fig. 2

   , = ,M + ,

5. SIMULATION RESULTS

   This section presents various simulation results of electrical characteristics of two stage op amp such as unity gain frequency, slew rate, Input common mode range, output and input offset voltages, power supply rejection ratio(PSRR) and output swing plots.

   , + = , + +

   , R

   ,

   ,

   1. Circuit schematic

      Fig. 3. Two stage miller compensated op-amp TABLE III

      ASPECT RATIOS

   2. Frequency response

      Fig.4. Frequency response of two stage op-amp

   3. DC Transfer Characteristics

      Device Name	(W/L) in µm through Design calculations	(W/L) in µm after optimization
      M1,M2	39.53 / 0.54	36.7 /0.54
      M3,M4	7.56 / 0.54	10 / 0.54
      M5	19.22 / 1	13 / 1
      M6	381.36 / 0.54	305 / 0.54
      M7	261.72 / 0.54	119 / 0.54
      M8	71.28 / 0.54	165 / 0.54
      M12-M13	–	13/1
      M14-M15	–	13/1
      M16	–	39/1
      M17	–	13/1

      Fig. 5. DC Transfer Characteristics of two stage opamp

   4. Output and input offset voltages

      Fig . 6. Output offset voltage of two stage opamp

      As seen from Fig. 6, the output offset of the amplifier is observed as 23.88 µV.

      And the Input offset voltage of the op amp is given by

      Input offset voltage = output offset voltage

      Open loop DC gain

      = 23.88 µV

      3536

      = 6.75nV

   5. Input Common Mode Range (ICMR):

      ICMR is measured as the range of voltages where the current through Id (M5) begins to saturate until output voltage follows the input voltage.

      Fig . 7. ICMR of two stage opamp

   6. Positive slew rate

      Fig . 8. Positive slew rate of two stage opamp

   7. Negative slew rate

      Fig . 9. Negative slew rate of two stage opamp

   8. Settling time ():

   Fig . 10. Settling time (ts) of two stage opamp

   1. Positive Power supply rejection ratio(P-PSRR)

      Fig . 11. (P-PSRR) of two stage opamp

   2. Negative Power supply rejection ratio(N-PSRR)

      Fig . 12. (N-PSRR) of two stage op amp

   3. Noise

   Fig. 12. Noise simulation of two stage op amp

   TABLE IIII PERFORMANCE SUMMARY

6. CONCLUSIONS

In this paper the design of single ended miller compensated two stage operational amplifier presented with detailed design calculations. Simulation results shows that op amp have open loop DC gain of 70.97dB , unity gain frequency of 120MHz and output swing voltage of 2 volts peak-to-peak. An op amp provides appropriate DC gain and output offset voltage of 23.88 µV to match the signal to the input range of ADC.

REFERENCES

1. George I Bourdopoulos, Aristodemos Pnevmatikakis, Vassilis Anastassopoulos and Theodore L Deliyannis Delta-Sigma Modulators

   – Modeling, Design and Applications Imperial college press, pp.102.

2. Phillip E Allen and Douglas R. Holdberg CMOS analog circuit design Oxford series, pp 243-280.

3. Design Procedure for Two-Stage CMOS OpampWith Flexible Noise- Power Balancing Scheme , Jirayuth Mahattanakul, Member, IEEE, and Jamorn Chutichatuporn, IEEE Transactions On Circuits And Systems I: Regular Papers, Vol. 52, No. 8, August 2005.

4. Analog Integrated Circuit Design by David A.Johns, Ken Martin, Wiley press, pp.248-249.

designs.

Mr. Prema Kumar. G received the B.Tech degree from Sri Venkateswara college of ngineering and Technology in Electronics and Communication Engineering and Master of Technology from University of Hyderabad in Integrated Circuits Technology.

His areas of interests include microelectronics and mixed-signal