DOI : 10.17577/IJERTCONV2IS08015
Ashna A, 2014, Design of sample and hold for 7 bit 100mhz flash ADC, INTERNATIONAL JOURNAL OF ENGINEERING RESEARCH & TECHNOLOGY (IJERT) NCETET – 2014 (Volume 2 – Issue 08),
- Open Access
- Total Downloads : 7
- Authors : Ashna A
- Paper ID : IJERTCONV2IS08015
- Volume & Issue : NCETET – 2014 (Volume 2 – Issue 08)
- Published (First Online): 30-07-2018
- ISSN (Online) : 2278-0181
- Publisher Name : IJERT
- License:
This work is licensed under a Creative Commons Attribution 4.0 International License
Text Only Version
Design of sample and hold for 7 bit 100mhz flash ADC