Design of Small-Gm Operational Tranconductance Amplifier in 0.18μm Technology

Design of Small-Gm Operational Tranconductance Amplifier in 0.18m Technology

Design of Small-Gm Operational Tranconductance Amplifier in 0.18m Technology

VIKRAM PALODIYA#1, SHWETA KARNIK #2, MAYANK SHRIVASTAVA #3, JITENDRA DODIYA#4.

#1, 2, Micro Electronics and VLSI design, #3,4. Digital Communication.

#1, 2 SGSITS, Indore, #3,4. PCST, Indore ( M.P. )India.

Abstract- This paper presents design concept of Small-Gm Operational Tran conductance Amplifier (OTA). The 0.18m CMOS process is used for Design and Simulation of this OTA. This OTA having a bias voltage 1.8 with supply voltage

1. V. The design and Simulation of this OTA is done using CADENCE Spectere environment with UMC 0.18m technology file. The Simulation results of this OTA shows that the open loop gain of about 76 dB which having Unity Gain Frequency of 90.25 MHz This OTA is having CMRR of 91dB and PSRR of 80dB. This OTA having power dissipation of 0.74 mW and Slew Rate 2.344 V/µsec.

   1. Due to recent development in VLSI technology the size of transistors decreases and power supply also decreases. The OTA is a basic building block in most of analogue circuit with linear input-output characteristics. The OTA is widely used in analogue circuit such as neural networks, Instrumentation amplifier, ADC and Filter circuit. The operational Transconductance Amplifier (OTA) is basically similar to conventional Operational Amplifiers in which both having Differential inputs. The basic difference between OTA and conventional operational Amplifier is that in OTA the output is in form of current but in conventional Op-Amps output is in form of Voltage. Small-Gm OTA using a current division technique is employed to small trans conductance, which needs only a small capacitor in HPF such that the integration on silicon is highly feasible

   2. Design of OTA: Figure 1 shows the schematic diagram of Small-Gm Operational Tran conductance Amplifier (OTA). In this OTA the supply voltage is Vdd= 1.8V. An ota usually has very smaller Gm. It is based on a current division voltage-to current converter technique, as shown in figure1. The source Drain voltage of MC1 is adjusted by tuning MC1s size such that MR1 and MR2 are biased in liner region. The differential voltage, (V1-V2) is converted to current, respectively flowing across MR1 and MR2. The sizes of MM_1 and MM_2 must

      be much larger than M1_1 and M1_2 such that the divided currents of M1_1 and M1_2 are smaller than the currents of MM_1 and MM_2. The Transistor M13 is an Output amplifier stage. The design parameters of this OTA are shown in below table I.

      There are several different OTAs are used in which this OTA is a simple OTA with low supply voltage and high gain. The OTA is characterized by various parameters like open loop gain, Bandwidth, Slew Rate, Noise and etc. The performance Measures are fixed Due to Design parameters such as Transistors size, Bias voltage and etc. In this paper we describe design of OTA amplifier and this design is done in 0.18m technology.

      Figure1:Small-GmOperationalTransconductance Amplifier

      TABLE I TRANSISTOR SIZE

      Device	W/L(m)
      M1,M2,M3	40/0.6
      M4,M5	20/0.6
      M6,M7,M8,M9	42/0.6
      M8,M9	50/0.6
      M10,M11	60/0.6
      M12,M13	0.8/0.6

   3. The design of this Small-Gm Operational Tran conductance Amplifier (OTA) is done using Cadence Tool. The Simulation results are done using Cadence Spectre environment using UMC 0.18 m CMOS technology. The simulation result of the OTA shows that the open loop gain of approximately 76 dB. The OTA has Unity Gain Frequency of about 90.25 MHz The Table II shows that the simulated results of the OTA. The AC response which shows gain and phase change with frequency is shown in figure 2. The variation in CMRR is shown in figure 3. Figure 4 shows the PSRR of This OTA. The simulated results of this OTA shows that PSRR of 80 dB and CMRR of 91 dB. Figure 5 shows the Layout of This OTA. DRC (Design Rule Check) is shown in figure 6. LVS (Layout versus schematic) and RCX is shown in figure 7, 8.

      TABLE II

      SIMULATED CHARACTERSTICS OF OTA

      S.NO.	Experimental	Results Value
      1	Open Loop Gain	76.83dB
      2	3dB Frequency	31.41kHz
      3	Unity Gain Frequency	90.25MHz
      4	Slew Rate	2.344V/usec
      5	Power Dissipation	0.74mW
      6	Load Capacitance	0.1pF
      7	PSRR	80dB
      8	CMRR	91dB

      Figure 2: Shows AC response which shows gain and phase change with frequency.

      Figure 3: Change in CMRR with frequency

      Figure 4: Change in PSRR with frequency

      Figure 5: Layout of OTA

      Figure 6: DRC (Design Rule Check) of OTA

      Figure 7: LVS (Layout versus Schematic) check

      Figure 8: RCX check

   4. CONCLUSION

      In this paper we present a Small-Gm Operational Tran conductance Amplifier (OTA) topology for low voltage and low power applications. This OTA can be used in low power, low voltage and high time constant applications such process controller, physical transducers and small battery operated devices. This work can be used in filter design, ADC design and instrumentation amplifiers because of its high gain, high CMRR and low power consumption.

   5. REFERENCES

1. J. H. Botma, R.F. Wassenaar, R. J. Wiegerink, A low voltage CMOS Op Amp with a rail-to-rail constant-gm input stage and a class AB rail-to-rail output stage, IEEE 1993 ISCAS, Chicago, pp.1314-1317.

2. Paul R. Gray, Paul L.Hurst, Stephan H.Lewis and Robort G.Mayer Analysis and design of analog integrated circuits,Forth Edition, John Wiley & sons, inc.2001, pp.425-439.

   Authors Profile: VIKRAM PALODIYA

   MTECH degree in Microelectronics

   and VLSI Design from SGSITS Indore 2011, working in the field of VLSI design. B.E degree in electronics and communication engineering in GEC Ujjain 2008 from Rajiv Gandhi technical university Bhopal

   SHWETA KARNIK

   Perusing MTECH degree in Microelectronics and VLSI Design from SGSITS Indore 2012, working in the field of VLSI Design. B.E degree in Bio- Medical Engineering from Rajiv Gandhi technical university Bhopal, INDIA in 2009.

3. Adel S. Sedra, Kenneth C.Smith Microelectronic Circuits, Oxford university press, Fourth edition ,2002,pp.89-91.

4. Jin Tao Li, Sio Hang Pun, Peng Un Mak and Mang I Vai Analysis of Op-Amp Power-Supply Current Sensing Current-Mode Instrumentation Amplifier for Biosignal Acquisition System,IEEE conference,August-2008,pp.2295-2298.

5. Y. Tsividis, Operation and Modelling of the MOS Transistor, 2nd ed. Boston, MA: McGraw-Hill, 1998.

6. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997.

7. Phillip E. Allen and Douglas R. Holberg CMOS analog circuit design ,second edition, Oxford university press, 2007,pp. 269-274.

MAYANK SHRIVASTVA

Perusing MTECH degree in Digital Communication from PCST Indore 2013, working in the field of digital design. B.E degree Electronics and Communication Engineering in IIST Indore 2009 from Rajiv Gandhi Technical University Bhopal.

JITENDRA DODIYA

Perusing MTECH degree in Digital Communication from PCST Indore 2013, working in the field of digital design. B.E degree Electronics and Communication Engineering in PCST Indore 2009 from Rajiv Gandhi Technical University Bhopal.