FPGA Based Hardware Implementation of Median Filtering and Morphological Image Processing Algorithm

FPGA Based Hardware Implementation of Median Filtering and Morphological Image Processing Algorithm

Shashi Maurya

Electronics & Communication EnggDept THDC Institute of Hydropower Engineering & Technology,Tehri,

Garhwal, UK India

Isha Gupta

School of Engineering and Technology, Noida International University, GautamBudh Nagar, UP, India

Abstract-Digital image processing is the processing and display of images. This field has wide number of applications each of which is useful in our everyday life. Various image processing algorithms help a user to clearly view the image and to be able to recognise different characteristics of the image. Median filtering is effective in removing salt and pepper noise from an image and morphological image processing algorithms like erosion and dilation are concerned with the shape analysis of the image. These two morphological operations help in image enhancement and their different combinations can yield many more useful processing algorithms. In this paper, implementation of these image processing algorithms on Xilinx Spartan 6 (Nexys 3) FPGA board is presented. The original gray scale image of size 200×150 is used and processed image is displayed on the VGA monitor. Hardware implementation is popular because they are efficient in terms of speed, complexity and offers parallelism and flexibility.

Keywords – dilation, erosion, FPGA, Median filtering, VGA.

I. INTRODUCTION

In the recent years, the area of digital image processing, is gaining immense importance with applications like medicine, space exploration, surveillance, authentication, automated industry, remote sensing, transportation and many more. One of the most important image processing operations is image enhancement. Image enhancement provides more effective display of image for visual interpretation. It helps a user to clearly view the image and to be able to recognise different characteristics of the image. This technique is very useful for assisting with distinction of different objects in an image. Image

enhancement deals largely with image correction, which may be necessary due to the image being affected by geometric distortion or noise. It can also remove blurring whereby a poor quality image may be upgraded to one with better quality and distinguishable features. [5]

For hardware implementation of image processing algorithms, FPGA has emerged as a viable target. This is because FPGA offers various advantages like it proves to be much more efficient in terms of cost and performance,offers parallelism performing various operations simultaneously, provides flexibility to reprogram or upgrade the design andcan speed up implementations by avoiding redundant operations. [1]

This paper focuses on image processing algorithms like median filtering and morphological image processing. Median filtering helps in removing impulsive noise from an image while preserving the edges. [9]. Morphological image processing includes two basic operations like Erosion and Dilation that help in enhancing the darker and lighter intensities in the image respectively. [3]

The original grayscale image of size 200×150 is first stored in Block ROM of the Spartan 6 FPGA and then the image processing algorithms are implemented using the 3×3 moving window technique being applied on each pixel using Xilinx ISE 12.1 and the processed pixels are stored in Block RAM of FPGA. Finally the original and processed images are displayed on the VGA (Video graphics array) monitor.

The following image processing algorithms are used:

1. Median filtering

   Median filter is a non-linear filter used in image processing for impulse noise removal while preserving the edges. The

   their neighbours. This filtering algorithm is applied by moving a mask on the input image from pixel to pixel. This

   encompassed by the neighbourhood. The mask can be of varying sizes like 3×3, 5×5, 7×7 etc. [8]. In non linear filtering instead of using linear algorithms certain different

   principal function of median filtering is to force points with distinct intensity levels to be more like

   mask selects a neighbourhood and applies a predefined operation on the image pixels

   operation is implemented on neighbourhood pixels to determine the centre or processed pixel value. This offers

   the advantage of not distorting the edges of original image while removing the noise.

   The response of median filter is based on ordering (ranking) the pixels contained in the image area

   encompassed by the filter and then replacing the centre pixel with the median value determined by ranking result.For a 3×3 neighbourhood the median value is the fifth largest value obtained by performing sorting of the 9 pixels

   Fig 1. Selecting median of series of values

   It can be used as a pre-processing technique in many image processing applications where the input image is affected by impulse noise that is caused by malfunctioning pixels in camera sensors, faulty memory locations in hardware or errors in data transmission. [5]

2. Morphological processing

   The word morphology is a combination of morphe, Greek for form or shape, and the suffix -ology, which means the study of. Consequently, the word morphology means the study of shapes. [5]

   Morphology refers to a branch of biology that deals with the form and structure of animals and plants. The same word is used in the context of mathematical morphology as a tool for extracting image components that are used in the representation and description of shape of the image [5].

   The two basic operations of morphological image processing are erosion and dilation.

   • Erosion

     It grows the darker intensities of the input image.Grayscale erosion can be achieved by ordering the pixels in the 3×3 neighbourhood selected by the mask and then picking up the minimum value from these pixels and replacing the centre pixel with this minimum value.Erosion can split apart joined objects and can strip away extrusions.

   • Dilation

   It grows the darker intensities of the input image. Grayscale dilation can be achieved by ordering the pixels in the 3×3 neighbourhood selected by the mask and then picking up the maximum value from these pixels and replacing the centre pixel with this maximum value. Dilation can repair breaks and intrusions in an image.

   Many other morphological image processing operations are obtained from the two basic operations erosion and dilation. Such operations are called as Compound Operations and can help in image enhancement, image segmentation,edge detection, feature generation, shape analysis and noise reduction.

   1. IMPLEMENTATION Fig 2 shows the block diagram of the proposed architecture.

      Fig 2 Proposed architecture of the system

      The process of building an image processing system that performs median filtering/morphological operations (erosion and dilation) is divided into two phases:

      1. FPGA implementation of VGA display with BROM as image memory

      2. FPGA implementation of morphological image processing.

      In the first phase the original image of size 240×160 is displayed on VGA screen which involves creating a .coe file in MATLAB, using Xilinx core generator for BROM and developing a VGA controller to set resolution.[6]

      The second phase involves taking an imageand performing median filtering and morphological image processing on that image using 3×3 window, and displaying input and processed image through VGA display.[4]

   2. RESULTS TABLE I

      FPGA	Median Filter +Morphological Operations(Erosion & Dilation)
      # Slices(18224)	396(2%)
      # Slice LUTs(9112)	1031(11%)
      # bonded IOBs(232)	15(6%)
      # BUFG/BUFGMUXs (16)	2(12%)
      # DCM/DCM_CLKGENs (4)	1(25%)
      Memory usage	178980 KB

   3. CONCLUSIONS AND FUTURE WORK

The successful implementation of morphological image processing operations like erosion and dilation and median filtering illustrates that a series of image processing algorithms useful for various applications can be efficiently implemented on FPGA hardware. This work can be used as a pre-processing task in many applications where it is useful to perform operations like noise removal, shape analysis, edge detection and many more.

The design could be extended to make it possible to generalize the implementation such that it can adapt automatically to different mask sizes, for example 5×5, 7×7 or 9×9 whichever is needed. This can be useful when operating large size images where bigger mask size is useful.

Much more morphological image processing operations and adaptive median filtering can be included. Also this work can be modified to fit to real time applications where the user can directly load the input image by interfacing FPGA with the camera.

REFERENCES

[1]. Implementation of Digital Image Morphological Algorithm on FPGA using Hardware Description Languages, R. Arunmozhi G. Mohan, International Journal of Computer Applications (0975 8887) Volume 57 No.5, November 2012.

[2]. F.M. Waltz and J.W.V. Miller, "Gray-scale image processing algorithms using finite-state machine concepts," Journal of ElectronicImaging, vol. 10, pp. 297-307, 2001.

[3]. An FPGA-based Architecture for Linear and Morphological image Filtering. Juan Manuel Ramirez, Emmanuel Morales Flores, Vicente Alarcon-Aquino, David Baez-Lopez,IEEE Electronics, Communications and Computer (CONIELECOMP), 20th International Conference, pp 90-95, 22-24 Feb 2010.

[4]. www.digilentinc.com (VGA controller reference design)

[5]. Rafael C. Gonzalez, Richard E. Woods, Digital Image Processing, Third edition, Pearson Prentice Hall, 2004.

[6]. FPGA Block RAM reference manual http://www.xilinx.com/support/documentation/application_notes/ xapp463.pdf

[7]. FPGA PROTOTYPING BY VHDL EXAMPLES Xilinx

SpartanTM-3 Version Pong P. Chu.

[8]. LEE, C. L., JEN, C. 1993. Binary Partition Algorithms and VLSI Architectures for Median and Rank Order Filtering, IEEE Transactions on signal processing, Vol. 41, No. 9

[9]. .Architecture Design for Median Filter, SubarnaChatterjee, Ajoy Kumar Ray, RezaulKarim, ArindamBiswas; Third National Conference on computer vision, pattern recognition, image processing and graphics,2011

[10]. C. T. Johnston, K. T. Gribbon and D. G. Bailey, Implementing Image Processing Algorithms on FPGAs, Proc. of the 11th Electronics New Zealand Conference (ENZCon '04), Palmerston North, New Zealand, November 2004.

[11]. MarekWnuk, Remarks on hardware implementation of image processing algorithms, Int. J. Appl. Math. Comput. Sci., vol. 18, March 2008